mirror of
https://github.com/team-infusion-developers/android_kernel_samsung_msm8976.git
synced 2024-10-31 18:09:19 +00:00
247a52e208
Wait for dma done interrupt before detaching iommu and turning off the clocks for static screen for command mode display. Currently on 8909 we wait for 4 VSYNC and if there is no new commit coming in then we turn off the clocks and detach iommu. Due to any reason if DMA transfer takes more than this much of time then the NOC errors will be seen as we are entering static screen while DMA is still active. Change-Id: Idf67545734115713d4f2c278b1acd417bade3527 Signed-off-by: Shivaraj Shetty <shivaraj@codeaurora.org>
359 lines
13 KiB
C
359 lines
13 KiB
C
/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef MDP3_HWIO_H
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#define MDP3_HWIO_H
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#include <linux/bitops.h>
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/*synchronization*/
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#define MDP3_REG_SYNC_CONFIG_0 0x0300
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#define MDP3_REG_SYNC_CONFIG_1 0x0304
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#define MDP3_REG_SYNC_CONFIG_2 0x0308
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#define MDP3_REG_SYNC_STATUS_0 0x030c
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#define MDP3_REG_SYNC_STATUS_1 0x0310
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#define MDP3_REG_SYNC_STATUS_2 0x0314
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#define MDP3_REG_PRIMARY_VSYNC_OUT_CTRL 0x0318
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#define MDP3_REG_SECONDARY_VSYNC_OUT_CTRL 0x031c
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#define MDP3_REG_EXTERNAL_VSYNC_OUT_CTRL 0x0320
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#define MDP3_REG_VSYNC_SEL 0x0324
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#define MDP3_REG_PRIMARY_VSYNC_INIT_VAL 0x0328
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#define MDP3_REG_SECONDARY_VSYNC_INIT_VAL 0x032c
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#define MDP3_REG_EXTERNAL_VSYNC_INIT_VAL 0x0330
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#define MDP3_REG_SYNC_THRESH_0 0x0200
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#define MDP3_REG_SYNC_THRESH_1 0x0204
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#define MDP3_REG_SYNC_THRESH_2 0x0208
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#define MDP3_REG_TEAR_CHECK_EN 0x020C
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#define MDP3_REG_PRIMARY_START_P0S 0x0210
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#define MDP3_REG_SECONDARY_START_POS 0x0214
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#define MDP3_REG_EXTERNAL_START_POS 0x0218
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/*interrupt*/
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#define MDP3_REG_INTR_ENABLE 0x0020
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#define MDP3_REG_INTR_STATUS 0x0024
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#define MDP3_REG_INTR_CLEAR 0x0028
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#define MDP3_REG_PRIMARY_RD_PTR_IRQ 0x021C
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#define MDP3_REG_SECONDARY_RD_PTR_IRQ 0x0220
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/*operation control*/
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#define MDP3_REG_DMA_P_START 0x0044
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#define MDP3_REG_DMA_S_START 0x0048
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#define MDP3_REG_DMA_E_START 0x004c
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#define MDP3_REG_DISPLAY_STATUS 0x0038
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#define MDP3_REG_HW_VERSION 0x0070
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#define MDP3_REG_SW_RESET 0x0074
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#define MDP3_REG_SEL_CLK_OR_HCLK_TEST_BUS 0x007C
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/*EBI*/
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#define MDP3_REG_EBI2_LCD0 0x003c
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#define MDP3_REG_EBI2_LCD0_YSTRIDE 0x0050
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/*clock control*/
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#define MDP3_REG_CGC_EN 0x0100
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#define MDP3_VBIF_REG_FORCE_EN 0x0004
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/* QOS Remapper */
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#define MDP3_DMA_P_QOS_REMAPPER 0x90090
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#define MDP3_DMA_P_WATERMARK_0 0x90094
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#define MDP3_DMA_P_WATERMARK_1 0x90098
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#define MDP3_DMA_P_WATERMARK_2 0x9009C
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#define MDP3_PANIC_ROBUST_CTRL 0x900A0
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#define MDP3_PANIC_LUT0 0x900A4
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#define MDP3_ROBUST_LUT 0x900AC
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/*danger safe*/
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#define MDP3_PANIC_ROBUST_CTRL 0x900A0
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/*DMA_P*/
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#define MDP3_REG_DMA_P_CONFIG 0x90000
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#define MDP3_REG_DMA_P_SIZE 0x90004
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#define MDP3_REG_DMA_P_IBUF_ADDR 0x90008
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#define MDP3_REG_DMA_P_IBUF_Y_STRIDE 0x9000C
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#define MDP3_REG_DMA_P_PROFILE_EN 0x90020
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#define MDP3_REG_DMA_P_OUT_XY 0x90010
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#define MDP3_REG_DMA_P_CURSOR_FORMAT 0x90040
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#define MDP3_REG_DMA_P_CURSOR_SIZE 0x90044
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#define MDP3_REG_DMA_P_CURSOR_BUF_ADDR 0x90048
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#define MDP3_REG_DMA_P_CURSOR_POS 0x9004c
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#define MDP3_REG_DMA_P_CURSOR_BLEND_CONFIG 0x90060
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#define MDP3_REG_DMA_P_CURSOR_BLEND_PARAM 0x90064
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#define MDP3_REG_DMA_P_CURSOR_BLEND_TRANS_MASK 0x90068
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#define MDP3_REG_DMA_P_COLOR_CORRECT_CONFIG 0x90070
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#define MDP3_REG_DMA_P_CSC_BYPASS 0X93004
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#define MDP3_REG_DMA_P_CSC_MV1 0x93400
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#define MDP3_REG_DMA_P_CSC_MV2 0x93440
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#define MDP3_REG_DMA_P_CSC_PRE_BV1 0x93500
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#define MDP3_REG_DMA_P_CSC_PRE_BV2 0x93540
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#define MDP3_REG_DMA_P_CSC_POST_BV1 0x93580
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#define MDP3_REG_DMA_P_CSC_POST_BV2 0x935c0
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#define MDP3_REG_DMA_P_CSC_PRE_LV1 0x93600
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#define MDP3_REG_DMA_P_CSC_PRE_LV2 0x93640
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#define MDP3_REG_DMA_P_CSC_POST_LV1 0x93680
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#define MDP3_REG_DMA_P_CSC_POST_LV2 0x936c0
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#define MDP3_REG_DMA_P_CSC_LUT1 0x93800
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#define MDP3_REG_DMA_P_CSC_LUT2 0x93c00
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#define MDP3_REG_DMA_P_HIST_START 0x94000
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#define MDP3_REG_DMA_P_HIST_FRAME_CNT 0x94004
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#define MDP3_REG_DMA_P_HIST_BIT_MASK 0x94008
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#define MDP3_REG_DMA_P_HIST_RESET_SEQ_START 0x9400c
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#define MDP3_REG_DMA_P_HIST_CONTROL 0x94010
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#define MDP3_REG_DMA_P_HIST_INTR_STATUS 0x94014
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#define MDP3_REG_DMA_P_HIST_INTR_CLEAR 0x94018
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#define MDP3_REG_DMA_P_HIST_INTR_ENABLE 0x9401c
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#define MDP3_REG_DMA_P_HIST_STOP_REQ 0x94020
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#define MDP3_REG_DMA_P_HIST_CANCEL_REQ 0x94024
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#define MDP3_REG_DMA_P_HIST_EXTRA_INFO_0 0x94028
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#define MDP3_REG_DMA_P_HIST_EXTRA_INFO_1 0x9402c
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#define MDP3_REG_DMA_P_HIST_R_DATA 0x94100
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#define MDP3_REG_DMA_P_HIST_G_DATA 0x94200
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#define MDP3_REG_DMA_P_HIST_B_DATA 0x94300
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#define MDP3_REG_DMA_P_FETCH_CFG 0x90074
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#define MDP3_REG_DMA_P_DCVS_CTRL 0x90080
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#define MDP3_REG_DMA_P_DCVS_STATUS 0x90084
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/*DMA_S*/
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#define MDP3_REG_DMA_S_CONFIG 0xA0000
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#define MDP3_REG_DMA_S_SIZE 0xA0004
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#define MDP3_REG_DMA_S_IBUF_ADDR 0xA0008
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#define MDP3_REG_DMA_S_IBUF_Y_STRIDE 0xA000C
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#define MDP3_REG_DMA_S_OUT_XY 0xA0010
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/*DMA MASK*/
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#define MDP3_DMA_IBUF_FORMAT_MASK 0x06000000
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#define MDP3_DMA_PACK_PATTERN_MASK 0x00003f00
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/*MISR*/
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#define MDP3_REG_MODE_CLK 0x000D0000
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#define MDP3_REG_MISR_RESET_CLK 0x000D0004
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#define MDP3_REG_EXPORT_MISR_CLK 0x000D0008
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#define MDP3_REG_MISR_CURR_VAL_CLK 0x000D000C
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#define MDP3_REG_MODE_HCLK 0x000D0100
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#define MDP3_REG_MISR_RESET_HCLK 0x000D0104
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#define MDP3_REG_EXPORT_MISR_HCLK 0x000D0108
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#define MDP3_REG_MISR_CURR_VAL_HCLK 0x000D010C
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#define MDP3_REG_MODE_DCLK 0x000D0200
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#define MDP3_REG_MISR_RESET_DCLK 0x000D0204
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#define MDP3_REG_EXPORT_MISR_DCLK 0x000D0208
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#define MDP3_REG_MISR_CURR_VAL_DCLK 0x000D020C
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#define MDP3_REG_CAPTURED_DCLK 0x000D0210
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#define MDP3_REG_MISR_CAPT_VAL_DCLK 0x000D0214
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#define MDP3_REG_MODE_TVCLK 0x000D0300
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#define MDP3_REG_MISR_RESET_TVCLK 0x000D0304
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#define MDP3_REG_EXPORT_MISR_TVCLK 0x000D0308
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#define MDP3_REG_MISR_CURR_VAL_TVCLK 0x000D030C
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#define MDP3_REG_CAPTURED_TVCLK 0x000D0310
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#define MDP3_REG_MISR_CAPT_VAL_TVCLK 0x000D0314
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/* Select DSI operation type(CMD/VIDEO) */
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#define MDP3_REG_MODE_DSI_PCLK 0x000D0400
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#define MDP3_REG_MODE_DSI_PCLK_BLOCK_DSI_CMD 0x10
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#define MDP3_REG_MODE_DSI_PCLK_BLOCK_DSI_VIDEO1 0x20
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#define MDP3_REG_MODE_DSI_PCLK_BLOCK_DSI_VIDEO2 0x30
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/* RESET DSI MISR STATE */
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#define MDP3_REG_MISR_RESET_DSI_PCLK 0x000D0404
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/* For reading MISR State(1) and driving data on test bus(0) */
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#define MDP3_REG_EXPORT_MISR_DSI_PCLK 0x000D0408
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/* Read MISR signature */
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#define MDP3_REG_MISR_CURR_VAL_DSI_PCLK 0x000D040C
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/* MISR status Bit0 (1) Capture Done */
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#define MDP3_REG_CAPTURED_DSI_PCLK 0x000D0410
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#define MDP3_REG_MISR_CAPT_VAL_DSI_PCLK 0x000D0414
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#define MDP3_REG_MISR_TESTBUS_CAPT_VAL 0x000D0600
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/*interface*/
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#define MDP3_REG_LCDC_EN 0xE0000
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#define MDP3_REG_LCDC_HSYNC_CTL 0xE0004
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#define MDP3_REG_LCDC_VSYNC_PERIOD 0xE0008
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#define MDP3_REG_LCDC_VSYNC_PULSE_WIDTH 0xE000C
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#define MDP3_REG_LCDC_DISPLAY_HCTL 0xE0010
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#define MDP3_REG_LCDC_DISPLAY_V_START 0xE0014
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#define MDP3_REG_LCDC_DISPLAY_V_END 0xE0018
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#define MDP3_REG_LCDC_ACTIVE_HCTL 0xE001C
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#define MDP3_REG_LCDC_ACTIVE_V_START 0xE0020
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#define MDP3_REG_LCDC_ACTIVE_V_END 0xE0024
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#define MDP3_REG_LCDC_BORDER_COLOR 0xE0028
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#define MDP3_REG_LCDC_UNDERFLOW_CTL 0xE002C
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#define MDP3_REG_LCDC_HSYNC_SKEW 0xE0030
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#define MDP3_REG_LCDC_TEST_CTL 0xE0034
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#define MDP3_REG_LCDC_CTL_POLARITY 0xE0038
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#define MDP3_REG_LCDC_TEST_COL_VAR1 0xE003C
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#define MDP3_REG_LCDC_TEST_COL_VAR2 0xE0040
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#define MDP3_REG_LCDC_UFLOW_HIDING_CTL 0xE0044
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#define MDP3_REG_LCDC_LOST_PIXEL_CNT_VALUE 0xE0048
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#define MDP3_REG_DSI_VIDEO_EN 0xF0000
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#define MDP3_REG_DSI_VIDEO_HSYNC_CTL 0xF0004
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#define MDP3_REG_DSI_VIDEO_VSYNC_PERIOD 0xF0008
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#define MDP3_REG_DSI_VIDEO_VSYNC_PULSE_WIDTH 0xF000C
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#define MDP3_REG_DSI_VIDEO_DISPLAY_HCTL 0xF0010
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#define MDP3_REG_DSI_VIDEO_DISPLAY_V_START 0xF0014
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#define MDP3_REG_DSI_VIDEO_DISPLAY_V_END 0xF0018
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#define MDP3_REG_DSI_VIDEO_ACTIVE_HCTL 0xF001C
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#define MDP3_REG_DSI_VIDEO_ACTIVE_V_START 0xF0020
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#define MDP3_REG_DSI_VIDEO_ACTIVE_V_END 0xF0024
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#define MDP3_REG_DSI_VIDEO_BORDER_COLOR 0xF0028
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#define MDP3_REG_DSI_VIDEO_UNDERFLOW_CTL 0xF002C
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#define MDP3_REG_DSI_VIDEO_HSYNC_SKEW 0xF0030
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#define MDP3_REG_DSI_VIDEO_TEST_CTL 0xF0034
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#define MDP3_REG_DSI_VIDEO_CTL_POLARITY 0xF0038
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#define MDP3_REG_DSI_VIDEO_TEST_COL_VAR1 0xF003C
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#define MDP3_REG_DSI_VIDEO_TEST_COL_VAR2 0xF0040
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#define MDP3_REG_DSI_VIDEO_UFLOW_HIDING_CTL 0xF0044
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#define MDP3_REG_DSI_VIDEO_LOST_PIXEL_CNT_VALUE 0xF0048
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#define MDP3_REG_DSI_CMD_MODE_ID_MAP 0xF1000
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#define MDP3_REG_DSI_CMD_MODE_TRIGGER_EN 0xF1004
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#define MDP3_PPP_CSC_PFMVn(n) (0x40400 + (4 * (n)))
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#define MDP3_PPP_CSC_PRMVn(n) (0x40440 + (4 * (n)))
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#define MDP3_PPP_CSC_PBVn(n) (0x40500 + (4 * (n)))
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#define MDP3_PPP_CSC_PLVn(n) (0x40580 + (4 * (n)))
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#define MDP3_PPP_CSC_SFMVn(n) (0x40480 + (4 * (n)))
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#define MDP3_PPP_CSC_SRMVn(n) (0x404C0 + (4 * (n)))
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#define MDP3_PPP_CSC_SBVn(n) (0x40540 + (4 * (n)))
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#define MDP3_PPP_CSC_SLVn(n) (0x405C0 + (4 * (n)))
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#define MDP3_PPP_SCALE_PHASEX_INIT 0x1013C
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#define MDP3_PPP_SCALE_PHASEY_INIT 0x10140
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#define MDP3_PPP_SCALE_PHASEX_STEP 0x10144
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#define MDP3_PPP_SCALE_PHASEY_STEP 0x10148
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#define MDP3_PPP_OP_MODE 0x10138
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#define MDP3_PPP_PRE_LUT 0x40800
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#define MDP3_PPP_POST_LUT 0x40C00
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#define MDP3_PPP_LUTn(n) ((4 * (n)))
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#define MDP3_PPP_BG_EDGE_REP 0x101BC
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#define MDP3_PPP_SRC_EDGE_REP 0x101B8
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#define MDP3_PPP_STRIDE_MASK 0x3FFF
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#define MDP3_PPP_STRIDE1_OFFSET 16
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#define MDP3_PPP_XY_MASK 0x0FFF
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#define MDP3_PPP_XY_OFFSET 16
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#define MDP3_PPP_SRC_SIZE 0x10108
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#define MDP3_PPP_SRCP0_ADDR 0x1010C
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#define MDP3_PPP_SRCP1_ADDR 0x10110
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#define MDP3_PPP_SRCP3_ADDR 0x10118
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#define MDP3_PPP_SRC_YSTRIDE1_ADDR 0x1011C
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#define MDP3_PPP_SRC_YSTRIDE2_ADDR 0x10120
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#define MDP3_PPP_SRC_FORMAT 0x10124
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#define MDP3_PPP_SRC_UNPACK_PATTERN1 0x10128
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#define MDP3_PPP_SRC_UNPACK_PATTERN2 0x1012C
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#define MDP3_PPP_OUT_FORMAT 0x10150
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#define MDP3_PPP_OUT_PACK_PATTERN1 0x10154
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#define MDP3_PPP_OUT_PACK_PATTERN2 0x10158
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#define MDP3_PPP_OUT_SIZE 0x10164
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#define MDP3_PPP_OUTP0_ADDR 0x10168
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#define MDP3_PPP_OUTP1_ADDR 0x1016C
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#define MDP3_PPP_OUTP3_ADDR 0x10174
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#define MDP3_PPP_OUT_YSTRIDE1_ADDR 0x10178
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#define MDP3_PPP_OUT_YSTRIDE2_ADDR 0x1017C
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#define MDP3_PPP_OUT_XY 0x1019C
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#define MDP3_PPP_BGP0_ADDR 0x101C0
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#define MDP3_PPP_BGP1_ADDR 0x101C4
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#define MDP3_PPP_BGP3_ADDR 0x101C8
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#define MDP3_PPP_BG_YSTRIDE1_ADDR 0x101CC
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#define MDP3_PPP_BG_YSTRIDE2_ADDR 0x101D0
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#define MDP3_PPP_BG_FORMAT 0x101D4
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#define MDP3_PPP_BG_UNPACK_PATTERN1 0x101D8
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#define MDP3_PPP_BG_UNPACK_PATTERN2 0x101DC
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#define MDP3_TFETCH_SOLID_FILL 0x20004
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#define MDP3_TFETCH_FILL_COLOR 0x20040
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#define MDP3_PPP_BLEND_PARAM 0x1014C
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#define MDP3_PPP_BLEND_BG_ALPHA_SEL 0x70010
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#define MDP3_PPP_ACTIVE BIT(0)
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/*interrupt mask*/
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#define MDP3_INTR_DP0_ROI_DONE_BIT BIT(0)
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#define MDP3_INTR_DP1_ROI_DONE_BIT BIT(1)
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#define MDP3_INTR_DMA_S_DONE_BIT BIT(2)
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#define MDP3_INTR_DMA_E_DONE_BIT BIT(3)
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#define MDP3_INTR_DP0_TERMINAL_FRAME_DONE_BIT BIT(4)
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#define MDP3_INTR_DP1_TERMINAL_FRAME_DONE_BIT BIT(5)
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#define MDP3_INTR_DMA_TV_DONE_BIT BIT(6)
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#define MDP3_INTR_TV_ENCODER_UNDER_RUN_BIT BIT(7)
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#define MDP3_INTR_SYNC_PRIMARY_LINE_BIT BIT(8)
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#define MDP3_INTR_SYNC_SECONDARY_LINE_BIT BIT(9)
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#define MDP3_INTR_SYNC_EXTERNAL_LINE_BIT BIT(10)
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#define MDP3_INTR_DP0_FETCH_DONE_BIT BIT(11)
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#define MDP3_INTR_DP1_FETCH_DONE_BIT BIT(12)
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#define MDP3_INTR_TV_OUT_FRAME_START_BIT BIT(13)
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#define MDP3_INTR_DMA_P_DONE_BIT BIT(14)
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#define MDP3_INTR_LCDC_START_OF_FRAME_BIT BIT(15)
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#define MDP3_INTR_LCDC_UNDERFLOW_BIT BIT(16)
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#define MDP3_INTR_DMA_P_LINE_BIT BIT(17)
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#define MDP3_INTR_DMA_S_LINE_BIT BIT(18)
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#define MDP3_INTR_DMA_E_LINE_BIT BIT(19)
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#define MDP3_INTR_DMA_P_HISTO_BIT BIT(20)
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#define MDP3_INTR_DTV_OUT_DONE_BIT BIT(21)
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#define MDP3_INTR_DTV_OUT_START_OF_FRAME_BIT BIT(22)
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#define MDP3_INTR_DTV_OUT_UNDERFLOW_BIT BIT(23)
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#define MDP3_INTR_DTV_OUT_LINE_BIT BIT(24)
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#define MDP3_INTR_DMA_P_AUTO_FREFRESH_START_BIT BIT(25)
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#define MDP3_INTR_DMA_S_AUTO_FREFRESH_START_BIT BIT(26)
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#define MDP3_INTR_QPIC_EOF_ENABLE_BIT BIT(27)
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enum {
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MDP3_INTR_DP0_ROI_DONE,
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MDP3_INTR_DP1_ROI_DONE,
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MDP3_INTR_DMA_S_DONE,
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MDP3_INTR_DMA_E_DONE,
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MDP3_INTR_DP0_TERMINAL_FRAME_DONE,
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MDP3_INTR_DP1_TERMINAL_FRAME_DONE,
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MDP3_INTR_DMA_TV_DONE,
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MDP3_INTR_TV_ENCODER_UNDER_RUN,
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MDP3_INTR_SYNC_PRIMARY_LINE,
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MDP3_INTR_SYNC_SECONDARY_LINE,
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MDP3_INTR_SYNC_EXTERNAL_LINE,
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MDP3_INTR_DP0_FETCH_DONE,
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MDP3_INTR_DP1_FETCH_DONE,
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MDP3_INTR_TV_OUT_FRAME_START,
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MDP3_INTR_DMA_P_DONE,
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MDP3_INTR_LCDC_START_OF_FRAME,
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MDP3_INTR_LCDC_UNDERFLOW,
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MDP3_INTR_DMA_P_LINE,
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MDP3_INTR_DMA_S_LINE,
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MDP3_INTR_DMA_E_LINE,
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MDP3_INTR_DMA_P_HISTO,
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MDP3_INTR_DTV_OUT_DONE,
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MDP3_INTR_DTV_OUT_START_OF_FRAME,
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MDP3_INTR_DTV_OUT_UNDERFLOW,
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MDP3_INTR_DTV_OUT_LINE,
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MDP3_INTR_DMA_P_AUTO_FREFRESH_START,
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MDP3_INTR_DMA_S_AUTO_FREFRESH_START,
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MDP3_INTR_QPIC_EOF_ENABLE,
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};
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#define MDP3_DMA_P_HIST_INTR_RESET_DONE_BIT BIT(0)
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#define MDP3_DMA_P_HIST_INTR_HIST_DONE_BIT BIT(1)
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#define MDP3_PPP_DONE MDP3_INTR_DP0_ROI_DONE
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#define MDP3_DMA_P_BUSY_BIT BIT(6)
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#endif /* MDP3_HWIO_H */
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