mirror of
https://github.com/team-infusion-developers/android_kernel_samsung_msm8976.git
synced 2024-10-31 18:09:19 +00:00
b608c815d9
Change irq interface provided by mdp from exporting symbols to function pointers. This will help in making mdp3 work with dsi 6G. Change-Id: I07a2acf56b75a2a6d83c0522d38efe3754bb8765 Signed-off-by: Shivaraj Shetty <shivaraj@codeaurora.org>
380 lines
9.8 KiB
C
380 lines
9.8 KiB
C
/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef MDSS_EDP_H
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#define MDSS_EDP_H
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#include <linux/of_gpio.h>
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#define edp_read(offset) readl_relaxed((offset))
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#define edp_write(offset, data) writel_relaxed((data), (offset))
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#define AUX_CMD_FIFO_LEN 144
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#define AUX_CMD_MAX 16
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#define AUX_CMD_I2C_MAX 128
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#define EDP_PORT_MAX 1
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#define EDP_SINK_CAP_LEN 16
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#define EDP_AUX_ERR_NONE 0
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#define EDP_AUX_ERR_ADDR -1
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#define EDP_AUX_ERR_TOUT -2
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#define EDP_AUX_ERR_NACK -3
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/* 4 bits of aux command */
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#define EDP_CMD_AUX_WRITE 0x8
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#define EDP_CMD_AUX_READ 0x9
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/* 4 bits of i2c command */
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#define EDP_CMD_I2C_MOT 0x4 /* i2c middle of transaction */
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#define EDP_CMD_I2C_WRITE 0x0
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#define EDP_CMD_I2C_READ 0x1
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#define EDP_CMD_I2C_STATUS 0x2 /* i2c write status request */
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/* cmd reply: bit 0, 1 for aux */
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#define EDP_AUX_ACK 0x0
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#define EDP_AUX_NACK 0x1
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#define EDP_AUX_DEFER 0x2
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/* cmd reply: bit 2, 3 for i2c */
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#define EDP_I2C_ACK 0x0
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#define EDP_I2C_NACK 0x4
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#define EDP_I2C_DEFER 0x8
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#define EDP_CMD_TIMEOUT 400 /* us */
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#define EDP_CMD_LEN 16
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#define EDP_INTR_ACK_SHIFT 1
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#define EDP_INTR_MASK_SHIFT 2
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#define EDP_MAX_LANE 4
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/* isr */
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#define EDP_INTR_HPD BIT(0)
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#define EDP_INTR_AUX_I2C_DONE BIT(3)
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#define EDP_INTR_WRONG_ADDR BIT(6)
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#define EDP_INTR_TIMEOUT BIT(9)
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#define EDP_INTR_NACK_DEFER BIT(12)
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#define EDP_INTR_WRONG_DATA_CNT BIT(15)
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#define EDP_INTR_I2C_NACK BIT(18)
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#define EDP_INTR_I2C_DEFER BIT(21)
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#define EDP_INTR_PLL_UNLOCKED BIT(24)
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#define EDP_INTR_AUX_ERROR BIT(27)
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#define EDP_INTR_STATUS1 \
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(EDP_INTR_HPD | EDP_INTR_AUX_I2C_DONE| \
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EDP_INTR_WRONG_ADDR | EDP_INTR_TIMEOUT | \
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EDP_INTR_NACK_DEFER | EDP_INTR_WRONG_DATA_CNT | \
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EDP_INTR_I2C_NACK | EDP_INTR_I2C_DEFER | \
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EDP_INTR_PLL_UNLOCKED | EDP_INTR_AUX_ERROR)
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#define EDP_INTR_MASK1 (EDP_INTR_STATUS1 << 2)
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#define EDP_INTR_READY_FOR_VIDEO BIT(0)
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#define EDP_INTR_IDLE_PATTERNs_SENT BIT(3)
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#define EDP_INTR_FRAME_END BIT(6)
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#define EDP_INTR_CRC_UPDATED BIT(9)
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#define EDP_INTR_STATUS2 \
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(EDP_INTR_READY_FOR_VIDEO | EDP_INTR_IDLE_PATTERNs_SENT | \
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EDP_INTR_FRAME_END | EDP_INTR_CRC_UPDATED)
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#define EDP_INTR_MASK2 (EDP_INTR_STATUS2 << 2)
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#define EDP_MAINLINK_CTRL 0x004
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#define EDP_STATE_CTRL 0x008
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#define EDP_MAINLINK_READY 0x084
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#define EDP_AUX_CTRL 0x300
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#define EDP_INTERRUPT_STATUS 0x308
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#define EDP_INTERRUPT_STATUS_2 0x30c
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#define EDP_AUX_DATA 0x314
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#define EDP_AUX_TRANS_CTRL 0x318
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#define EDP_AUX_STATUS 0x324
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#define EDP_PHY_EDPPHY_GLB_VM_CFG0 0x510
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#define EDP_PHY_EDPPHY_GLB_VM_CFG1 0x514
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struct edp_cmd {
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char read; /* 1 == read, 0 == write */
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char i2c; /* 1 == i2c cmd, 0 == native cmd */
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u32 addr; /* 20 bits */
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char *datap;
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int len; /* len to be tx OR len to be rx for read */
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char next; /* next command */
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};
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struct edp_buf {
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char *start; /* buffer start addr */
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char *end; /* buffer end addr */
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int size; /* size of buffer */
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char *data; /* data pointer */
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int len; /* dara length */
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char trans_num; /* transaction number */
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char i2c; /* 1 == i2c cmd, 0 == native cmd */
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};
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#define DPCD_ENHANCED_FRAME BIT(0)
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#define DPCD_TPS3 BIT(1)
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#define DPCD_MAX_DOWNSPREAD_0_5 BIT(2)
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#define DPCD_NO_AUX_HANDSHAKE BIT(3)
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#define DPCD_PORT_0_EDID_PRESENTED BIT(4)
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/* event */
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#define EV_EDP_AUX_SETUP BIT(0)
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#define EV_EDID_READ BIT(1)
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#define EV_DPCD_CAP_READ BIT(2)
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#define EV_DPCD_STATUS_READ BIT(3)
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#define EV_LINK_TRAIN BIT(4)
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#define EV_IDLE_PATTERNS_SENT BIT(30)
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#define EV_VIDEO_READY BIT(31)
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/* edp state ctrl */
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#define ST_TRAIN_PATTERN_1 BIT(0)
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#define ST_TRAIN_PATTERN_2 BIT(1)
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#define ST_TRAIN_PATTERN_3 BIT(2)
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#define ST_SYMBOL_ERR_RATE_MEASUREMENT BIT(3)
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#define ST_PRBS7 BIT(4)
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#define ST_CUSTOM_80_BIT_PATTERN BIT(5)
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#define ST_SEND_VIDEO BIT(6)
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#define ST_PUSH_IDLE BIT(7)
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/* sink power state */
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#define SINK_POWER_ON 1
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#define SINK_POWER_OFF 2
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#define EDP_LINK_RATE_162 6 /* 1.62G = 270M * 6 */
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#define EDP_LINK_RATE_270 10 /* 2.70G = 270M * 10 */
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#define EDP_LINK_RATE_MAX EDP_LINK_RATE_270
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struct dpcd_cap {
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char major;
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char minor;
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char max_lane_count;
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char num_rx_port;
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char i2c_speed_ctrl;
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char scrambler_reset;
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char enhanced_frame;
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u32 max_link_rate; /* 162, 270 and 540 Mb, divided by 10 */
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u32 flags;
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u32 rx_port0_buf_size;
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u32 training_read_interval;/* us */
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};
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struct dpcd_link_status {
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char lane_01_status;
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char lane_23_status;
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char interlane_align_done;
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char downstream_port_status_changed;
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char link_status_updated;
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char port_0_in_sync;
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char port_1_in_sync;
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char req_voltage_swing[4];
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char req_pre_emphasis[4];
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};
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struct display_timing_desc {
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u32 pclk;
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u32 h_addressable; /* addressable + boder = active */
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u32 h_border;
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u32 h_blank; /* fporch + bporch + sync_pulse = blank */
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u32 h_fporch;
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u32 h_sync_pulse;
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u32 v_addressable; /* addressable + boder = active */
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u32 v_border;
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u32 v_blank; /* fporch + bporch + sync_pulse = blank */
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u32 v_fporch;
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u32 v_sync_pulse;
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u32 width_mm;
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u32 height_mm;
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u32 interlaced;
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u32 stereo;
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u32 sync_type;
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u32 sync_separate;
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u32 vsync_pol;
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u32 hsync_pol;
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};
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#define EDID_DISPLAY_PORT_SUPPORT 0x05
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struct edp_edid {
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char id_name[4];
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short id_product;
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char version;
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char revision;
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char video_intf; /* edp == 0x5 */
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char color_depth; /* 6, 8, 10, 12 and 14 bits */
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char color_format; /* RGB 4:4:4, YCrCb 4:4:4, Ycrcb 4:2:2 */
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char dpm; /* display power management */
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char sync_digital; /* 1 = digital */
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char sync_separate; /* 1 = separate */
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char vsync_pol; /* 0 = negative, 1 = positive */
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char hsync_pol; /* 0 = negative, 1 = positive */
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char ext_block_cnt;
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struct display_timing_desc timing[4];
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};
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struct edp_statistic {
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u32 intr_hpd;
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u32 intr_aux_i2c_done;
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u32 intr_wrong_addr;
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u32 intr_tout;
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u32 intr_nack_defer;
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u32 intr_wrong_data_cnt;
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u32 intr_i2c_nack;
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u32 intr_i2c_defer;
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u32 intr_pll_unlock;
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u32 intr_crc_update;
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u32 intr_frame_end;
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u32 intr_idle_pattern_sent;
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u32 intr_ready_for_video;
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u32 aux_i2c_tx;
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u32 aux_i2c_rx;
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u32 aux_native_tx;
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u32 aux_native_rx;
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};
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#define DPCD_LINK_VOLTAGE_MAX 4
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#define DPCD_LINK_PRE_EMPHASIS_MAX 4
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#define HPD_EVENT_MAX 8
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struct mdss_edp_drv_pdata {
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/* device driver */
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int (*on) (struct mdss_panel_data *pdata);
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int (*off) (struct mdss_panel_data *pdata);
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struct platform_device *pdev;
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struct mutex emutex;
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int clk_cnt;
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int cont_splash;
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bool inited;
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int delay_link_train;
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/* edp specific */
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unsigned char *base;
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int base_size;
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unsigned char *mmss_cc_base;
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u32 mask1;
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u32 mask2;
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struct mdss_panel_data panel_data;
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struct mdss_util_intf *mdss_util;
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int edp_on_cnt;
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int edp_off_cnt;
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u32 pixel_rate;
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u32 aux_rate;
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char link_rate; /* X 27000000 for real rate */
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char lane_cnt;
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char train_link_rate; /* X 27000000 for real rate */
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char train_lane_cnt;
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struct edp_edid edid;
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struct dpcd_cap dpcd;
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/* regulators */
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struct regulator *vdda_vreg;
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/* clocks */
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struct clk *aux_clk;
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struct clk *pixel_clk;
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struct clk *ahb_clk;
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struct clk *link_clk;
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struct clk *mdp_core_clk;
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int clk_on;
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/* gpios */
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int gpio_panel_en;
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int gpio_lvl_en;
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/* backlight */
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struct pwm_device *bl_pwm;
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bool is_pwm_enabled;
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int lpg_channel;
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int pwm_period;
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/* hpd */
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int gpio_panel_hpd;
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enum of_gpio_flags hpd_flags;
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int hpd_irq;
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/* aux */
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struct completion aux_comp;
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struct completion train_comp;
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struct completion idle_comp;
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struct completion video_comp;
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struct mutex aux_mutex;
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struct mutex train_mutex;
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u32 aux_cmd_busy;
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u32 aux_cmd_i2c;
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int aux_trans_num;
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int aux_error_num;
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u32 aux_ctrl_reg;
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struct edp_buf txp;
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struct edp_buf rxp;
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char txbuf[256];
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char rxbuf[256];
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struct dpcd_link_status link_status;
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char v_level;
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char p_level;
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/* transfer unit */
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char tu_desired;
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char valid_boundary;
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char delay_start;
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u32 bpp;
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struct edp_statistic edp_stat;
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/* event */
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wait_queue_head_t event_q;
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u32 event_pndx;
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u32 event_gndx;
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u32 event_todo_list[HPD_EVENT_MAX];
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spinlock_t event_lock;
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spinlock_t lock;
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};
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int mdss_edp_aux_clk_enable(struct mdss_edp_drv_pdata *edp_drv);
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void mdss_edp_aux_clk_disable(struct mdss_edp_drv_pdata *edp_drv);
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int mdss_edp_clk_enable(struct mdss_edp_drv_pdata *edp_drv);
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void mdss_edp_clk_disable(struct mdss_edp_drv_pdata *edp_drv);
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int mdss_edp_clk_init(struct mdss_edp_drv_pdata *edp_drv);
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void mdss_edp_clk_deinit(struct mdss_edp_drv_pdata *edp_drv);
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int mdss_edp_prepare_aux_clocks(struct mdss_edp_drv_pdata *edp_drv);
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void mdss_edp_unprepare_aux_clocks(struct mdss_edp_drv_pdata *edp_drv);
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int mdss_edp_prepare_clocks(struct mdss_edp_drv_pdata *edp_drv);
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void mdss_edp_unprepare_clocks(struct mdss_edp_drv_pdata *edp_drv);
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void mdss_edp_dpcd_cap_read(struct mdss_edp_drv_pdata *edp);
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int mdss_edp_dpcd_status_read(struct mdss_edp_drv_pdata *edp);
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void mdss_edp_edid_read(struct mdss_edp_drv_pdata *edp, int block);
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int mdss_edp_link_train(struct mdss_edp_drv_pdata *edp);
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void edp_aux_i2c_handler(struct mdss_edp_drv_pdata *edp, u32 isr);
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void edp_aux_native_handler(struct mdss_edp_drv_pdata *edp, u32 isr);
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void mdss_edp_aux_init(struct mdss_edp_drv_pdata *ep);
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void mdss_edp_fill_link_cfg(struct mdss_edp_drv_pdata *ep);
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void mdss_edp_sink_power_down(struct mdss_edp_drv_pdata *ep);
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void mdss_edp_state_ctrl(struct mdss_edp_drv_pdata *ep, u32 state);
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int mdss_edp_sink_power_state(struct mdss_edp_drv_pdata *ep, char state);
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void mdss_edp_lane_power_ctrl(struct mdss_edp_drv_pdata *ep, int up);
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void mdss_edp_config_ctrl(struct mdss_edp_drv_pdata *ep);
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void mdss_edp_clk_debug(unsigned char *edp_base, unsigned char *mmss_cc_base);
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#endif /* MDSS_EDP_H */
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