mirror of
https://github.com/team-infusion-developers/android_kernel_samsung_msm8976.git
synced 2024-10-31 18:09:19 +00:00
a9426b6f17
For power saving, only turn on qpic_a_clk before accessing registers, turn it off after accessing is done. Change-Id: Icdd316781cc2cd3ba55995d49020760d73fb41ca Signed-off-by: Ken Zhang <kenz@codeaurora.org>
821 lines
20 KiB
C
821 lines
20 KiB
C
/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/time.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <linux/hrtimer.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/debugfs.h>
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#include <linux/delay.h>
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#include <linux/mutex.h>
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#include <linux/regulator/consumer.h>
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#include <linux/semaphore.h>
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#include <linux/uaccess.h>
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#include <linux/bootmem.h>
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#include <linux/dma-mapping.h>
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#include <linux/clk/msm-clk.h>
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#include <linux/msm-sps.h>
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#include <linux/msm-bus.h>
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#include <mach/hardware.h>
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#include "mdss_fb.h"
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#include "mdss_qpic.h"
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#include "mdss_qpic_panel.h"
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static int mdss_qpic_probe(struct platform_device *pdev);
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static int mdss_qpic_remove(struct platform_device *pdev);
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static void qpic_interrupt_en(u32 en);
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struct qpic_data_type *qpic_res;
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/* for debugging */
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static u32 use_bam = true;
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static u32 use_irq = true;
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static u32 use_vsync = true;
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static const struct of_device_id mdss_qpic_dt_match[] = {
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{ .compatible = "qcom,mdss_qpic",},
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{}
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};
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MODULE_DEVICE_TABLE(of, mdss_qpic_dt_match);
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static struct platform_driver mdss_qpic_driver = {
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.probe = mdss_qpic_probe,
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.remove = mdss_qpic_remove,
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.shutdown = NULL,
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.driver = {
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/*
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* Simulate mdp hw
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*/
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.name = "mdp",
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.of_match_table = mdss_qpic_dt_match,
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},
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};
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int qpic_on(struct msm_fb_data_type *mfd)
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{
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int ret;
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if (qpic_res->qpic_a_clk)
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clk_prepare_enable(qpic_res->qpic_a_clk);
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if ((!qpic_res->lk_transition_done) &&
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(QPIC_INP(QPIC_REG_QPIC_LCDC_CTRL) & (1 << 8))) {
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qpic_res->splash_screen_transition = true;
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qpic_res->panel_io.splash_screen_transition = true;
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}
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ret = mdss_qpic_panel_on(qpic_res->panel_data, &qpic_res->panel_io);
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qpic_res->qpic_is_on = true;
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if (!qpic_res->lk_transition_done) {
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qpic_res->splash_screen_transition = false;
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qpic_res->panel_io.splash_screen_transition = false;
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qpic_res->lk_transition_done = true;
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}
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if (qpic_res->qpic_a_clk)
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clk_disable_unprepare(qpic_res->qpic_a_clk);
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return ret;
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}
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int qpic_off(struct msm_fb_data_type *mfd)
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{
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int ret;
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if (qpic_res->qpic_a_clk)
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clk_prepare_enable(qpic_res->qpic_a_clk);
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ret = mdss_qpic_panel_off(qpic_res->panel_data, &qpic_res->panel_io);
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if (use_irq)
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qpic_interrupt_en(false);
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if (qpic_res->qpic_a_clk)
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clk_disable_unprepare(qpic_res->qpic_a_clk);
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qpic_res->qpic_is_on = false;
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return ret;
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}
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static int msm_qpic_bus_set_vote(u32 vote)
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{
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int ret;
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if (!qpic_res->bus_handle)
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return 0;
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ret = msm_bus_scale_client_update_request(qpic_res->bus_handle,
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vote);
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if (ret)
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pr_err("msm_bus_scale_client_update_request() failed, bus_handle=0x%x, vote=%d, err=%d\n",
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qpic_res->bus_handle, vote, ret);
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return ret;
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}
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static void mdss_qpic_pan_display(struct msm_fb_data_type *mfd)
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{
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struct fb_info *fbi;
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u32 offset, fb_offset, size;
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int bpp;
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if (!mfd) {
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pr_err("%s: mfd is NULL!", __func__);
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return;
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}
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if (!qpic_res->qpic_is_on) {
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pr_err("Panel is not on\n");
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return;
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}
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fbi = mfd->fbi;
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bpp = fbi->var.bits_per_pixel / 8;
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offset = fbi->var.xoffset * bpp +
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fbi->var.yoffset * fbi->fix.line_length;
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if (offset > fbi->fix.smem_len) {
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pr_err("invalid fb offset=%u total length=%u\n",
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offset, fbi->fix.smem_len);
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return;
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}
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if (use_bam)
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fb_offset = (u32)fbi->fix.smem_start + offset;
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else
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fb_offset = (u32)mfd->fbi->screen_base + offset;
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msm_qpic_bus_set_vote(1);
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size = fbi->var.xres * fbi->var.yres * bpp;
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if (qpic_res->qpic_a_clk)
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clk_prepare_enable(qpic_res->qpic_a_clk);
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qpic_send_frame(0, 0, fbi->var.xres - 1, fbi->var.yres - 1,
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(u32 *)fb_offset, size);
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if (qpic_res->qpic_a_clk)
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clk_disable_unprepare(qpic_res->qpic_a_clk);
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msm_qpic_bus_set_vote(0);
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}
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int mdss_qpic_alloc_fb_mem(struct msm_fb_data_type *mfd)
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{
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size_t size;
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u32 yres = mfd->fbi->var.yres_virtual;
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size = PAGE_ALIGN(mfd->fbi->fix.line_length * yres);
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if (!qpic_res->res_init)
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return -EINVAL;
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if (mfd->index != 0) {
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mfd->fbi->fix.smem_start = 0;
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mfd->fbi->screen_base = NULL;
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mfd->fbi->fix.smem_len = 0;
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mfd->iova = 0;
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return 0;
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}
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if (!qpic_res->fb_virt) {
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qpic_res->fb_virt = (void *)dmam_alloc_coherent(
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&qpic_res->pdev->dev,
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size,
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&qpic_res->fb_phys,
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GFP_KERNEL);
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pr_debug("%s size=%d vir_addr=%x phys_addr=%x",
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__func__, size, (int)qpic_res->fb_virt,
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(int)qpic_res->fb_phys);
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if (!qpic_res->fb_virt) {
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pr_err("%s fb allocation failed", __func__);
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return -ENOMEM;
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}
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}
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if (!qpic_res->cmd_buf_virt) {
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qpic_res->cmd_buf_virt = dma_alloc_writecombine(
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NULL, QPIC_MAX_CMD_BUF_SIZE,
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&qpic_res->cmd_buf_phys, GFP_KERNEL);
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pr_debug("%s cmd_buf virt=%x phys=%x", __func__,
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(int)qpic_res->cmd_buf_virt,
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qpic_res->cmd_buf_phys);
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if (!qpic_res->cmd_buf_virt) {
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pr_err("%s cmd buf allocation failed", __func__);
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return -ENOMEM;
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}
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}
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mfd->fbi->fix.smem_start = qpic_res->fb_phys;
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mfd->fbi->screen_base = qpic_res->fb_virt;
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mfd->fbi->fix.smem_len = size;
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mfd->iova = 0;
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return 0;
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}
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u32 mdss_qpic_fb_stride(u32 fb_index, u32 xres, int bpp)
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{
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return xres * bpp;
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}
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int mdss_qpic_overlay_init(struct msm_fb_data_type *mfd)
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{
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struct msm_mdp_interface *qpic_interface = &mfd->mdp;
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qpic_interface->on_fnc = qpic_on;
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qpic_interface->off_fnc = qpic_off;
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qpic_interface->do_histogram = NULL;
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qpic_interface->cursor_update = NULL;
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qpic_interface->dma_fnc = mdss_qpic_pan_display;
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qpic_interface->ioctl_handler = NULL;
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qpic_interface->kickoff_fnc = NULL;
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return 0;
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}
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int qpic_register_panel(struct mdss_panel_data *pdata)
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{
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struct platform_device *mdss_fb_dev = NULL;
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int rc;
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mdss_fb_dev = platform_device_alloc("mdss_fb", pdata->panel_info.pdest);
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if (!mdss_fb_dev) {
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pr_err("unable to allocate mdss_fb device\n");
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return -ENOMEM;
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}
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mdss_fb_dev->dev.platform_data = pdata;
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rc = platform_device_add(mdss_fb_dev);
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if (rc) {
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platform_device_put(mdss_fb_dev);
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pr_err("unable to probe mdss_fb device (%d)\n", rc);
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return rc;
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}
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qpic_res->panel_data = pdata;
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return rc;
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}
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int qpic_init_sps(struct platform_device *pdev,
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struct qpic_sps_endpt *end_point)
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{
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int rc = 0;
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struct sps_pipe *pipe_handle;
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struct sps_connect *sps_config = &end_point->config;
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struct sps_register_event *sps_event = &end_point->bam_event;
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struct sps_bam_props bam = {0};
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unsigned long bam_handle = 0;
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if (qpic_res->sps_init)
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return 0;
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bam.phys_addr = qpic_res->qpic_phys + 0x4000;
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bam.virt_addr = qpic_res->qpic_base + 0x4000;
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bam.irq = qpic_res->irq - 4;
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bam.manage = SPS_BAM_MGR_DEVICE_REMOTE | SPS_BAM_MGR_MULTI_EE;
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rc = sps_phy2h(bam.phys_addr, &bam_handle);
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if (rc)
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rc = sps_register_bam_device(&bam, &bam_handle);
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if (rc) {
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pr_err("%s bam_handle is NULL", __func__);
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rc = -ENOMEM;
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goto out;
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}
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pipe_handle = sps_alloc_endpoint();
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if (!pipe_handle) {
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pr_err("sps_alloc_endpoint() failed\n");
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rc = -ENOMEM;
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goto out;
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}
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rc = sps_get_config(pipe_handle, sps_config);
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if (rc) {
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pr_err("sps_get_config() failed %d\n", rc);
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goto free_endpoint;
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}
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/* WRITE CASE: source - system memory; destination - BAM */
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sps_config->source = SPS_DEV_HANDLE_MEM;
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sps_config->destination = bam_handle;
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sps_config->mode = SPS_MODE_DEST;
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sps_config->dest_pipe_index = 6;
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sps_config->options = SPS_O_AUTO_ENABLE | SPS_O_EOT;
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sps_config->lock_group = 0;
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/*
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* Descriptor FIFO is a cyclic FIFO. If 64 descriptors
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* are allowed to be submitted before we get any ack for any of them,
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* the descriptor FIFO size should be: (SPS_MAX_DESC_NUM + 1) *
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* sizeof(struct sps_iovec).
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*/
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sps_config->desc.size = (64) *
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sizeof(struct sps_iovec);
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sps_config->desc.base = dmam_alloc_coherent(&pdev->dev,
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sps_config->desc.size,
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&sps_config->desc.phys_base,
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GFP_KERNEL);
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if (!sps_config->desc.base) {
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pr_err("dmam_alloc_coherent() failed for size %x\n",
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sps_config->desc.size);
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rc = -ENOMEM;
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goto free_endpoint;
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}
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memset(sps_config->desc.base, 0x00, sps_config->desc.size);
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rc = sps_connect(pipe_handle, sps_config);
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if (rc) {
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pr_err("sps_connect() failed %d\n", rc);
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goto free_endpoint;
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}
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init_completion(&end_point->completion);
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sps_event->mode = SPS_TRIGGER_WAIT;
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sps_event->options = SPS_O_EOT;
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sps_event->xfer_done = &end_point->completion;
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sps_event->user = (void *)qpic_res;
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rc = sps_register_event(pipe_handle, sps_event);
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if (rc) {
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pr_err("sps_register_event() failed %d\n", rc);
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goto sps_disconnect;
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}
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end_point->handle = pipe_handle;
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qpic_res->sps_init = true;
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goto out;
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sps_disconnect:
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sps_disconnect(pipe_handle);
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free_endpoint:
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sps_free_endpoint(pipe_handle);
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out:
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return rc;
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}
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void mdss_qpic_reset(void)
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{
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u32 time_end;
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QPIC_OUTP(QPIC_REG_QPIC_LCDC_RESET, 1 << 0);
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/* wait 100 us after reset as suggested by hw */
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usleep(100);
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time_end = (u32)ktime_to_ms(ktime_get()) +
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QPIC_MAX_VSYNC_WAIT_TIME;
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while (((QPIC_INP(QPIC_REG_QPIC_LCDC_STTS) & (1 << 8)) == 0)) {
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if ((u32)ktime_to_ms(ktime_get()) > time_end) {
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pr_err("%s reset not finished", __func__);
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break;
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}
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/* yield 100 us for next polling by experiment*/
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usleep(100);
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}
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}
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static void qpic_interrupt_en(u32 en)
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{
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QPIC_OUTP(QPIC_REG_QPIC_LCDC_IRQ_CLR, 0xff);
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if (en) {
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if (!qpic_res->irq_ena) {
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init_completion(&qpic_res->fifo_eof_comp);
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qpic_res->irq_ena = true;
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enable_irq(qpic_res->irq);
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}
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} else {
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QPIC_OUTP(QPIC_REG_QPIC_LCDC_IRQ_EN, 0);
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disable_irq(qpic_res->irq);
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qpic_res->irq_ena = false;
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}
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}
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static irqreturn_t qpic_irq_handler(int irq, void *ptr)
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{
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u32 data;
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data = QPIC_INP(QPIC_REG_QPIC_LCDC_IRQ_STTS);
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QPIC_OUTP(QPIC_REG_QPIC_LCDC_IRQ_CLR, 0xff);
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QPIC_OUTP(QPIC_REG_QPIC_LCDC_IRQ_EN, 0);
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if (data & ((1 << 2) | (1 << 4)))
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complete(&qpic_res->fifo_eof_comp);
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return IRQ_HANDLED;
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}
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static int qpic_send_pkt_bam(u32 cmd, u32 len, u8 *param)
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{
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int ret = 0;
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u32 phys_addr, cfg2, block_len , flags;
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if ((cmd != OP_WRITE_MEMORY_START) &&
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(cmd != OP_WRITE_MEMORY_CONTINUE)) {
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memcpy((u8 *)qpic_res->cmd_buf_virt, param, len);
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phys_addr = qpic_res->cmd_buf_phys;
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} else {
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phys_addr = (u32)param;
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}
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cfg2 = QPIC_INP(QPIC_REG_QPIC_LCDC_CFG2);
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cfg2 &= ~0xFF;
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cfg2 |= cmd;
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QPIC_OUTP(QPIC_REG_QPIC_LCDC_CFG2, cfg2);
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block_len = 0x7FF0;
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while (len > 0) {
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if (len <= 0x7FF0) {
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flags = SPS_IOVEC_FLAG_EOT;
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block_len = len;
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} else {
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flags = 0;
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}
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ret = sps_transfer_one(qpic_res->qpic_endpt.handle,
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phys_addr, block_len, NULL, flags);
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if (ret)
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pr_err("failed to submit command %x ret %d\n",
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cmd, ret);
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phys_addr += block_len;
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len -= block_len;
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}
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ret = wait_for_completion_timeout(
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&qpic_res->qpic_endpt.completion,
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msecs_to_jiffies(100 * 4));
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if (ret <= 0)
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pr_err("%s timeout %x", __func__, ret);
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else
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ret = 0;
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return ret;
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}
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void qpic_dump_reg(void)
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{
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pr_info("%s\n", __func__);
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pr_info("QPIC_REG_QPIC_LCDC_CTRL = %x\n",
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QPIC_INP(QPIC_REG_QPIC_LCDC_CTRL));
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pr_info("QPIC_REG_QPIC_LCDC_CMD_DATA_CYCLE_CNT = %x\n",
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QPIC_INP(QPIC_REG_QPIC_LCDC_CMD_DATA_CYCLE_CNT));
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pr_info("QPIC_REG_QPIC_LCDC_CFG0 = %x\n",
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QPIC_INP(QPIC_REG_QPIC_LCDC_CFG0));
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pr_info("QPIC_REG_QPIC_LCDC_CFG1 = %x\n",
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QPIC_INP(QPIC_REG_QPIC_LCDC_CFG1));
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pr_info("QPIC_REG_QPIC_LCDC_CFG2 = %x\n",
|
|
QPIC_INP(QPIC_REG_QPIC_LCDC_CFG2));
|
|
pr_info("QPIC_REG_QPIC_LCDC_IRQ_EN = %x\n",
|
|
QPIC_INP(QPIC_REG_QPIC_LCDC_IRQ_EN));
|
|
pr_info("QPIC_REG_QPIC_LCDC_IRQ_STTS = %x\n",
|
|
QPIC_INP(QPIC_REG_QPIC_LCDC_IRQ_STTS));
|
|
pr_info("QPIC_REG_QPIC_LCDC_STTS = %x\n",
|
|
QPIC_INP(QPIC_REG_QPIC_LCDC_STTS));
|
|
pr_info("QPIC_REG_QPIC_LCDC_FIFO_SOF = %x\n",
|
|
QPIC_INP(QPIC_REG_QPIC_LCDC_FIFO_SOF));
|
|
}
|
|
|
|
static int qpic_wait_for_fifo(void)
|
|
{
|
|
u32 data, time_end;
|
|
int ret = 0;
|
|
|
|
if (use_irq) {
|
|
data = QPIC_INP(QPIC_REG_QPIC_LCDC_STTS);
|
|
data &= 0x3F;
|
|
if (data == 0)
|
|
return ret;
|
|
INIT_COMPLETION(qpic_res->fifo_eof_comp);
|
|
QPIC_OUTP(QPIC_REG_QPIC_LCDC_IRQ_EN, (1 << 4));
|
|
ret = wait_for_completion_timeout(&qpic_res->fifo_eof_comp,
|
|
msecs_to_jiffies(QPIC_MAX_VSYNC_WAIT_TIME));
|
|
if (ret > 0) {
|
|
ret = 0;
|
|
} else {
|
|
pr_err("%s timeout %x\n", __func__, ret);
|
|
ret = -ETIMEDOUT;
|
|
}
|
|
QPIC_OUTP(QPIC_REG_QPIC_LCDC_IRQ_EN, 0);
|
|
} else {
|
|
time_end = (u32)ktime_to_ms(ktime_get()) +
|
|
QPIC_MAX_VSYNC_WAIT_TIME;
|
|
while (1) {
|
|
data = QPIC_INP(QPIC_REG_QPIC_LCDC_STTS);
|
|
data &= 0x3F;
|
|
if (data == 0)
|
|
break;
|
|
/* yield 10 us for next polling by experiment*/
|
|
usleep(10);
|
|
if (ktime_to_ms(ktime_get()) > time_end) {
|
|
pr_err("%s time out", __func__);
|
|
ret = -EBUSY;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static int qpic_wait_for_eof(void)
|
|
{
|
|
u32 data, time_end;
|
|
int ret = 0;
|
|
if (use_irq) {
|
|
data = QPIC_INP(QPIC_REG_QPIC_LCDC_IRQ_STTS);
|
|
if (data & (1 << 2))
|
|
return ret;
|
|
INIT_COMPLETION(qpic_res->fifo_eof_comp);
|
|
QPIC_OUTP(QPIC_REG_QPIC_LCDC_IRQ_EN, (1 << 2));
|
|
ret = wait_for_completion_timeout(&qpic_res->fifo_eof_comp,
|
|
msecs_to_jiffies(QPIC_MAX_VSYNC_WAIT_TIME));
|
|
if (ret > 0) {
|
|
ret = 0;
|
|
} else {
|
|
pr_err("%s timeout %x\n", __func__, ret);
|
|
ret = -ETIMEDOUT;
|
|
}
|
|
QPIC_OUTP(QPIC_REG_QPIC_LCDC_IRQ_EN, 0);
|
|
} else {
|
|
time_end = (u32)ktime_to_ms(ktime_get()) +
|
|
QPIC_MAX_VSYNC_WAIT_TIME;
|
|
while (1) {
|
|
data = QPIC_INP(QPIC_REG_QPIC_LCDC_IRQ_STTS);
|
|
if (data & (1 << 2))
|
|
break;
|
|
/* yield 10 us for next polling by experiment*/
|
|
usleep(10);
|
|
if (ktime_to_ms(ktime_get()) > time_end) {
|
|
pr_err("%s wait for eof time out\n", __func__);
|
|
qpic_dump_reg();
|
|
ret = -EBUSY;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static int qpic_send_pkt_sw(u32 cmd, u32 len, u8 *param)
|
|
{
|
|
u32 bytes_left, space, data, cfg2;
|
|
int i, ret = 0;
|
|
if (len <= 4) {
|
|
len = (len + 3) / 4; /* len in dwords */
|
|
data = 0;
|
|
if (param) {
|
|
for (i = 0; i < len; i++)
|
|
data |= (u32)param[i] << (8 * i);
|
|
}
|
|
QPIC_OUTP(QPIC_REG_QPIC_LCDC_CMD_DATA_CYCLE_CNT, len);
|
|
QPIC_OUTP(QPIC_REG_LCD_DEVICE_CMD0 + (4 * cmd), data);
|
|
return 0;
|
|
}
|
|
|
|
if ((len & 0x1) != 0) {
|
|
pr_debug("%s: number of bytes needs be even", __func__);
|
|
len = (len + 1) & (~0x1);
|
|
}
|
|
QPIC_OUTP(QPIC_REG_QPIC_LCDC_IRQ_CLR, 0xff);
|
|
QPIC_OUTP(QPIC_REG_QPIC_LCDC_CMD_DATA_CYCLE_CNT, 0);
|
|
cfg2 = QPIC_INP(QPIC_REG_QPIC_LCDC_CFG2);
|
|
if ((cmd != OP_WRITE_MEMORY_START) &&
|
|
(cmd != OP_WRITE_MEMORY_CONTINUE))
|
|
cfg2 |= (1 << 24); /* transparent mode */
|
|
else
|
|
cfg2 &= ~(1 << 24);
|
|
|
|
cfg2 &= ~0xFF;
|
|
cfg2 |= cmd;
|
|
QPIC_OUTP(QPIC_REG_QPIC_LCDC_CFG2, cfg2);
|
|
QPIC_OUTP(QPIC_REG_QPIC_LCDC_FIFO_SOF, 0x0);
|
|
bytes_left = len;
|
|
|
|
while (bytes_left > 0) {
|
|
ret = qpic_wait_for_fifo();
|
|
if (ret)
|
|
goto exit_send_cmd_sw;
|
|
|
|
space = 16;
|
|
|
|
while ((space > 0) && (bytes_left > 0)) {
|
|
/* write to fifo */
|
|
if (bytes_left >= 4) {
|
|
QPIC_OUTP(QPIC_REG_QPIC_LCDC_FIFO_DATA_PORT0,
|
|
*(u32 *)param);
|
|
param += 4;
|
|
bytes_left -= 4;
|
|
space--;
|
|
} else if (bytes_left == 2) {
|
|
QPIC_OUTPW(QPIC_REG_QPIC_LCDC_FIFO_DATA_PORT0,
|
|
*(u16 *)param);
|
|
bytes_left -= 2;
|
|
}
|
|
}
|
|
}
|
|
/* finished */
|
|
QPIC_OUTP(QPIC_REG_QPIC_LCDC_FIFO_EOF, 0x0);
|
|
ret = qpic_wait_for_eof();
|
|
exit_send_cmd_sw:
|
|
cfg2 &= ~(1 << 24);
|
|
QPIC_OUTP(QPIC_REG_QPIC_LCDC_CFG2, cfg2);
|
|
return ret;
|
|
}
|
|
|
|
int qpic_send_pkt(u32 cmd, u8 *param, u32 len)
|
|
{
|
|
if (!use_bam || ((cmd != OP_WRITE_MEMORY_CONTINUE) &&
|
|
(cmd != OP_WRITE_MEMORY_START)))
|
|
return qpic_send_pkt_sw(cmd, len, param);
|
|
else
|
|
return qpic_send_pkt_bam(cmd, len, param);
|
|
}
|
|
|
|
int mdss_qpic_init(void)
|
|
{
|
|
int ret = 0;
|
|
u32 data;
|
|
|
|
if (!qpic_res->splash_screen_transition)
|
|
mdss_qpic_reset();
|
|
|
|
pr_info("%s version=%x", __func__, QPIC_INP(QPIC_REG_LCDC_VERSION));
|
|
data = QPIC_INP(QPIC_REG_QPIC_LCDC_CTRL);
|
|
/* clear vsync wait , bam mode = 0*/
|
|
data &= ~(3 << 0);
|
|
data &= ~(0x1f << 3);
|
|
data |= (1 << 3); /* threshold */
|
|
data |= (1 << 8); /* lcd_en */
|
|
data &= ~(0x1f << 9);
|
|
data |= (1 << 9); /* threshold */
|
|
QPIC_OUTP(QPIC_REG_QPIC_LCDC_CTRL, data);
|
|
|
|
if (use_irq && (!qpic_res->irq_requested)) {
|
|
ret = devm_request_irq(&qpic_res->pdev->dev,
|
|
qpic_res->irq, qpic_irq_handler,
|
|
IRQF_DISABLED, "QPIC", qpic_res);
|
|
if (ret) {
|
|
pr_err("qpic request_irq() failed!\n");
|
|
use_irq = false;
|
|
} else {
|
|
disable_irq(qpic_res->irq);
|
|
}
|
|
qpic_res->irq_requested = true;
|
|
}
|
|
|
|
qpic_interrupt_en(use_irq);
|
|
|
|
QPIC_OUTP(QPIC_REG_QPIC_LCDC_CFG0, 0x02108501);
|
|
data = QPIC_INP(QPIC_REG_QPIC_LCDC_CFG2);
|
|
data &= ~(0xFFF);
|
|
data |= 0x200; /* XRGB */
|
|
data |= 0x2C;
|
|
QPIC_OUTP(QPIC_REG_QPIC_LCDC_CFG2, data);
|
|
|
|
if (use_bam) {
|
|
qpic_init_sps(qpic_res->pdev , &qpic_res->qpic_endpt);
|
|
data = QPIC_INP(QPIC_REG_QPIC_LCDC_CTRL);
|
|
data |= (1 << 1);
|
|
QPIC_OUTP(QPIC_REG_QPIC_LCDC_CTRL, data);
|
|
}
|
|
/* TE enable */
|
|
if (use_vsync) {
|
|
data = QPIC_INP(QPIC_REG_QPIC_LCDC_CTRL);
|
|
data |= (1 << 0);
|
|
QPIC_OUTP(QPIC_REG_QPIC_LCDC_CTRL, data);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
u32 qpic_read_data(u32 cmd_index, u32 size)
|
|
{
|
|
u32 data = 0;
|
|
if (size <= 4) {
|
|
QPIC_OUTP(QPIC_REG_QPIC_LCDC_CMD_DATA_CYCLE_CNT, size);
|
|
data = QPIC_INP(QPIC_REG_LCD_DEVICE_CMD0 + (cmd_index * 4));
|
|
}
|
|
return data;
|
|
}
|
|
|
|
static int msm_qpic_bus_register(struct platform_device *pdev)
|
|
{
|
|
int ret = 0;
|
|
struct msm_bus_scale_pdata *use_cases;
|
|
|
|
use_cases = msm_bus_cl_get_pdata(pdev);
|
|
if (!use_cases) {
|
|
pr_err("msm_bus_cl_get_pdata failed\n");
|
|
return -EINVAL;
|
|
}
|
|
qpic_res->bus_handle =
|
|
msm_bus_scale_register_client(use_cases);
|
|
if (!qpic_res->bus_handle) {
|
|
ret = -EINVAL;
|
|
pr_err("msm_bus_scale_register_client failed\n");
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static int mdss_qpic_probe(struct platform_device *pdev)
|
|
{
|
|
struct resource *res;
|
|
int rc = 0;
|
|
static struct msm_mdp_interface qpic_interface = {
|
|
.init_fnc = mdss_qpic_overlay_init,
|
|
.fb_mem_alloc_fnc = mdss_qpic_alloc_fb_mem,
|
|
.fb_stride = mdss_qpic_fb_stride,
|
|
};
|
|
|
|
if (!pdev->dev.of_node) {
|
|
pr_err("qpic driver only supports device tree probe\n");
|
|
return -ENOTSUPP;
|
|
}
|
|
|
|
if (!qpic_res)
|
|
qpic_res = devm_kzalloc(&pdev->dev,
|
|
sizeof(*qpic_res), GFP_KERNEL);
|
|
|
|
if (!qpic_res)
|
|
return -ENOMEM;
|
|
|
|
if (qpic_res->res_init) {
|
|
pr_err("qpic already initialized\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
pdev->id = 0;
|
|
|
|
qpic_res->pdev = pdev;
|
|
platform_set_drvdata(pdev, qpic_res);
|
|
|
|
res = platform_get_resource_byname(pdev,
|
|
IORESOURCE_MEM, "qpic_base");
|
|
if (!res) {
|
|
pr_err("unable to get QPIC reg base address\n");
|
|
rc = -ENOMEM;
|
|
goto probe_done;
|
|
}
|
|
|
|
qpic_res->qpic_reg_size = resource_size(res);
|
|
qpic_res->qpic_base = devm_ioremap(&pdev->dev, res->start,
|
|
qpic_res->qpic_reg_size);
|
|
if (unlikely(!qpic_res->qpic_base)) {
|
|
pr_err("unable to map MDSS QPIC base\n");
|
|
rc = -ENOMEM;
|
|
goto probe_done;
|
|
}
|
|
qpic_res->qpic_phys = res->start;
|
|
pr_info("MDSS QPIC HW Base phy_Address=0x%x virt=0x%x\n",
|
|
(int) res->start, (int) qpic_res->qpic_base);
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
|
if (!res) {
|
|
pr_err("unable to get QPIC irq\n");
|
|
rc = -ENOMEM;
|
|
goto probe_done;
|
|
}
|
|
qpic_res->qpic_a_clk = clk_get(&pdev->dev, "core_a_clk");
|
|
if (IS_ERR(qpic_res->qpic_a_clk)) {
|
|
pr_err("%s: Can't find core_a_clk", __func__);
|
|
qpic_res->qpic_a_clk = NULL;
|
|
rc = -EPERM;
|
|
goto probe_done;
|
|
}
|
|
|
|
qpic_res->irq = res->start;
|
|
qpic_res->res_init = true;
|
|
|
|
mdss_qpic_panel_io_init(pdev, &qpic_res->panel_io);
|
|
|
|
rc = mdss_fb_register_mdp_instance(&qpic_interface);
|
|
if (rc)
|
|
pr_err("unable to register QPIC instance\n");
|
|
|
|
msm_qpic_bus_register(pdev);
|
|
probe_done:
|
|
return rc;
|
|
}
|
|
|
|
static int mdss_qpic_remove(struct platform_device *pdev)
|
|
{
|
|
if (qpic_res->bus_handle)
|
|
msm_bus_scale_unregister_client(qpic_res->bus_handle);
|
|
qpic_res->bus_handle = 0;
|
|
return 0;
|
|
}
|
|
|
|
static int __init mdss_qpic_driver_init(void)
|
|
{
|
|
int ret;
|
|
|
|
ret = platform_driver_register(&mdss_qpic_driver);
|
|
if (ret)
|
|
pr_err("mdss_qpic_register_driver() failed!\n");
|
|
return ret;
|
|
}
|
|
|
|
module_init(mdss_qpic_driver_init);
|
|
|
|
|