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f78eae2e6f
The scheduling domain hierarchy is:
all cpus -->
cpus that share an instruction cache -->
cpus that share an integer execution unit
Signed-off-by: David S. Miller <davem@davemloft.net>
19 lines
601 B
C
19 lines
601 B
C
#ifndef _ASM_SPARC64_TOPOLOGY_H
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#define _ASM_SPARC64_TOPOLOGY_H
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#ifdef CONFIG_SMP
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#include <asm/spitfire.h>
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#define topology_physical_package_id(cpu) (cpu_data(cpu).proc_id)
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#define topology_core_id(cpu) (cpu_data(cpu).core_id)
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#define topology_core_siblings(cpu) (cpu_core_map[cpu])
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#define topology_thread_siblings(cpu) (cpu_sibling_map[cpu])
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#define mc_capable() (tlb_type == hypervisor)
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#define smt_capable() (tlb_type == hypervisor)
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#endif /* CONFIG_SMP */
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#include <asm-generic/topology.h>
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#define cpu_coregroup_map(cpu) (cpu_core_map[cpu])
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#endif /* _ASM_SPARC64_TOPOLOGY_H */
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