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https://github.com/team-infusion-developers/android_kernel_samsung_msm8976.git
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f80dff9da0
get_irqnr_preamble allows machines to take some action before entering the get_irqnr_and_base loop. On iop we enable cp6 access. arch_ret_to_user is added to the userspace return path to allow individual architectures to take actions, like disabling coprocessor access, before the final return to userspace. Per Nicolas Pitre's note, there is no need to cp_wait on the return to user as the latency to return is sufficient. Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
137 lines
3.8 KiB
ArmAsm
137 lines
3.8 KiB
ArmAsm
/*
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* include/asm-arm/arch-lh7a40x/entry-macro.S
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*
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* Low-level IRQ helper macros for LH7A40x platforms
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <asm/hardware.h>
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#include <asm/arch/irqs.h>
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/* In order to allow there to be support for both of the processor
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classes at the same time, we make a hack here that isn't very
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pretty. At startup, the link pointed to with the
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branch_irq_lh7a400 symbol is replaced with a NOP when the CPU is
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detected as a lh7a404.
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*** FIXME: we should clean this up so that there is only one
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implementation for each CPU's design.
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*/
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#if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404)
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.macro disable_fiq
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.endm
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.macro get_irqnr_preamble, base, tmp
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.endm
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.macro arch_ret_to_user, tmp1, tmp2
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.endm
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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branch_irq_lh7a400: b 1000f
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@ Implementation of the LH7A404 get_irqnr_and_base.
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mov \irqnr, #0 @ VIC1 irq base
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mov \base, #io_p2v(0x80000000) @ APB registers
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add \base, \base, #0x8000
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ldr \tmp, [\base, #0x0030] @ VIC1_VECTADDR
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tst \tmp, #VA_VECTORED @ Direct vectored
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bne 1002f
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tst \tmp, #VA_VIC1DEFAULT @ Default vectored VIC1
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ldrne \irqstat, [\base, #0] @ VIC1_IRQSTATUS
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bne 1001f
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add \base, \base, #(0xa000 - 0x8000)
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ldr \tmp, [\base, #0x0030] @ VIC2_VECTADDR
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tst \tmp, #VA_VECTORED @ Direct vectored
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bne 1002f
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ldr \irqstat, [\base, #0] @ VIC2_IRQSTATUS
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mov \irqnr, #32 @ VIC2 irq base
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1001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry
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bcs 1008f @ Bit set; irq found
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add \irqnr, \irqnr, #1
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bne 1001b @ Until no bits
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b 1009f @ Nothing? Hmm.
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1002: and \irqnr, \tmp, #0x3f @ Mask for valid bits
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1008: movs \irqstat, #1 @ Force !Z
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str \tmp, [\base, #0x0030] @ Clear vector
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b 1009f
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@ Implementation of the LH7A400 get_irqnr_and_base.
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1000: mov \irqnr, #0
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mov \base, #io_p2v(0x80000000) @ APB registers
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ldr \irqstat, [\base, #0x500] @ PIC INTSR
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1001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry
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bcs 1008f @ Bit set; irq found
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add \irqnr, \irqnr, #1
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bne 1001b @ Until no bits
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b 1009f @ Nothing? Hmm.
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1008: movs \irqstat, #1 @ Force !Z
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1009:
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.endm
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#elif defined (CONFIG_ARCH_LH7A400)
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.macro disable_fiq
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.endm
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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mov \irqnr, #0
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mov \base, #io_p2v(0x80000000) @ APB registers
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ldr \irqstat, [\base, #0x500] @ PIC INTSR
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1001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry
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bcs 1008f @ Bit set; irq found
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add \irqnr, \irqnr, #1
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bne 1001b @ Until no bits
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b 1009f @ Nothing? Hmm.
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1008: movs \irqstat, #1 @ Force !Z
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1009:
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.endm
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#elif defined(CONFIG_ARCH_LH7A404)
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.macro disable_fiq
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.endm
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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mov \irqnr, #0 @ VIC1 irq base
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mov \base, #io_p2v(0x80000000) @ APB registers
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add \base, \base, #0x8000
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ldr \tmp, [\base, #0x0030] @ VIC1_VECTADDR
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tst \tmp, #VA_VECTORED @ Direct vectored
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bne 1002f
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tst \tmp, #VA_VIC1DEFAULT @ Default vectored VIC1
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ldrne \irqstat, [\base, #0] @ VIC1_IRQSTATUS
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bne 1001f
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add \base, \base, #(0xa000 - 0x8000)
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ldr \tmp, [\base, #0x0030] @ VIC2_VECTADDR
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tst \tmp, #VA_VECTORED @ Direct vectored
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bne 1002f
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ldr \irqstat, [\base, #0] @ VIC2_IRQSTATUS
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mov \irqnr, #32 @ VIC2 irq base
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1001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry
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bcs 1008f @ Bit set; irq found
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add \irqnr, \irqnr, #1
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bne 1001b @ Until no bits
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b 1009f @ Nothing? Hmm.
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1002: and \irqnr, \tmp, #0x3f @ Mask for valid bits
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1008: movs \irqstat, #1 @ Force !Z
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str \tmp, [\base, #0x0030] @ Clear vector
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1009:
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.endm
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#endif
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