mirror of
https://github.com/team-infusion-developers/android_kernel_samsung_msm8976.git
synced 2024-11-07 04:09:21 +00:00
1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
538 lines
18 KiB
C
538 lines
18 KiB
C
/*
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* drivers/net/gianfar.h
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*
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* Gianfar Ethernet Driver
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* Driver for FEC on MPC8540 and TSEC on MPC8540/MPC8560
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* Based on 8260_io/fcc_enet.c
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*
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* Author: Andy Fleming
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* Maintainer: Kumar Gala (kumar.gala@freescale.com)
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*
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* Copyright (c) 2002-2004 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* Still left to do:
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* -Add support for module parameters
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* -Add support for ethtool -s
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* -Add patch for ethtool phys id
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*/
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#ifndef __GIANFAR_H
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#define __GIANFAR_H
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#include <linux/config.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/string.h>
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#include <linux/errno.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/skbuff.h>
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#include <linux/spinlock.h>
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#include <linux/mm.h>
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#include <linux/fsl_devices.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/uaccess.h>
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#include <linux/module.h>
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#include <linux/version.h>
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#include <linux/crc32.h>
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#include <linux/workqueue.h>
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#include <linux/ethtool.h>
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#include <linux/netdevice.h>
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#include "gianfar_phy.h"
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/* The maximum number of packets to be handled in one call of gfar_poll */
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#define GFAR_DEV_WEIGHT 64
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/* Number of bytes to align the rx bufs to */
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#define RXBUF_ALIGNMENT 64
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/* The number of bytes which composes a unit for the purpose of
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* allocating data buffers. ie-for any given MTU, the data buffer
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* will be the next highest multiple of 512 bytes. */
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#define INCREMENTAL_BUFFER_SIZE 512
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#define MAC_ADDR_LEN 6
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#define PHY_INIT_TIMEOUT 100000
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#define GFAR_PHY_CHANGE_TIME 2
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#define DEVICE_NAME "%s: Gianfar Ethernet Controller Version 1.1, "
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#define DRV_NAME "gfar-enet"
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extern const char gfar_driver_name[];
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extern const char gfar_driver_version[];
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/* These need to be powers of 2 for this driver */
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#ifdef CONFIG_GFAR_NAPI
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#define DEFAULT_TX_RING_SIZE 256
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#define DEFAULT_RX_RING_SIZE 256
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#else
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#define DEFAULT_TX_RING_SIZE 64
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#define DEFAULT_RX_RING_SIZE 64
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#endif
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#define GFAR_RX_MAX_RING_SIZE 256
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#define GFAR_TX_MAX_RING_SIZE 256
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#define DEFAULT_RX_BUFFER_SIZE 1536
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#define TX_RING_MOD_MASK(size) (size-1)
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#define RX_RING_MOD_MASK(size) (size-1)
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#define JUMBO_BUFFER_SIZE 9728
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#define JUMBO_FRAME_SIZE 9600
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/* Latency of interface clock in nanoseconds */
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/* Interface clock latency , in this case, means the
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* time described by a value of 1 in the interrupt
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* coalescing registers' time fields. Since those fields
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* refer to the time it takes for 64 clocks to pass, the
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* latencies are as such:
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* GBIT = 125MHz => 8ns/clock => 8*64 ns / tick
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* 100 = 25 MHz => 40ns/clock => 40*64 ns / tick
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* 10 = 2.5 MHz => 400ns/clock => 400*64 ns / tick
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*/
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#define GFAR_GBIT_TIME 512
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#define GFAR_100_TIME 2560
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#define GFAR_10_TIME 25600
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#define DEFAULT_TX_COALESCE 1
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#define DEFAULT_TXCOUNT 16
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#define DEFAULT_TXTIME 400
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#define DEFAULT_RX_COALESCE 1
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#define DEFAULT_RXCOUNT 16
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#define DEFAULT_RXTIME 400
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#define TBIPA_VALUE 0x1f
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#define MIIMCFG_INIT_VALUE 0x00000007
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#define MIIMCFG_RESET 0x80000000
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#define MIIMIND_BUSY 0x00000001
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/* MAC register bits */
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#define MACCFG1_SOFT_RESET 0x80000000
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#define MACCFG1_RESET_RX_MC 0x00080000
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#define MACCFG1_RESET_TX_MC 0x00040000
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#define MACCFG1_RESET_RX_FUN 0x00020000
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#define MACCFG1_RESET_TX_FUN 0x00010000
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#define MACCFG1_LOOPBACK 0x00000100
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#define MACCFG1_RX_FLOW 0x00000020
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#define MACCFG1_TX_FLOW 0x00000010
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#define MACCFG1_SYNCD_RX_EN 0x00000008
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#define MACCFG1_RX_EN 0x00000004
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#define MACCFG1_SYNCD_TX_EN 0x00000002
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#define MACCFG1_TX_EN 0x00000001
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#define MACCFG2_INIT_SETTINGS 0x00007205
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#define MACCFG2_FULL_DUPLEX 0x00000001
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#define MACCFG2_IF 0x00000300
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#define MACCFG2_MII 0x00000100
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#define MACCFG2_GMII 0x00000200
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#define MACCFG2_HUGEFRAME 0x00000020
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#define MACCFG2_LENGTHCHECK 0x00000010
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#define ECNTRL_INIT_SETTINGS 0x00001000
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#define ECNTRL_TBI_MODE 0x00000020
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#define MRBLR_INIT_SETTINGS DEFAULT_RX_BUFFER_SIZE
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#define MINFLR_INIT_SETTINGS 0x00000040
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/* Init to do tx snooping for buffers and descriptors */
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#define DMACTRL_INIT_SETTINGS 0x000000c3
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#define DMACTRL_GRS 0x00000010
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#define DMACTRL_GTS 0x00000008
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#define TSTAT_CLEAR_THALT 0x80000000
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/* Interrupt coalescing macros */
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#define IC_ICEN 0x80000000
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#define IC_ICFT_MASK 0x1fe00000
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#define IC_ICFT_SHIFT 21
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#define mk_ic_icft(x) \
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(((unsigned int)x << IC_ICFT_SHIFT)&IC_ICFT_MASK)
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#define IC_ICTT_MASK 0x0000ffff
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#define mk_ic_ictt(x) (x&IC_ICTT_MASK)
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#define mk_ic_value(count, time) (IC_ICEN | \
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mk_ic_icft(count) | \
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mk_ic_ictt(time))
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#define RCTRL_PROM 0x00000008
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#define RSTAT_CLEAR_RHALT 0x00800000
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#define IEVENT_INIT_CLEAR 0xffffffff
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#define IEVENT_BABR 0x80000000
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#define IEVENT_RXC 0x40000000
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#define IEVENT_BSY 0x20000000
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#define IEVENT_EBERR 0x10000000
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#define IEVENT_MSRO 0x04000000
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#define IEVENT_GTSC 0x02000000
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#define IEVENT_BABT 0x01000000
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#define IEVENT_TXC 0x00800000
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#define IEVENT_TXE 0x00400000
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#define IEVENT_TXB 0x00200000
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#define IEVENT_TXF 0x00100000
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#define IEVENT_LC 0x00040000
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#define IEVENT_CRL 0x00020000
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#define IEVENT_XFUN 0x00010000
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#define IEVENT_RXB0 0x00008000
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#define IEVENT_GRSC 0x00000100
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#define IEVENT_RXF0 0x00000080
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#define IEVENT_RX_MASK (IEVENT_RXB0 | IEVENT_RXF0)
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#define IEVENT_TX_MASK (IEVENT_TXB | IEVENT_TXF)
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#define IEVENT_ERR_MASK \
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(IEVENT_RXC | IEVENT_BSY | IEVENT_EBERR | IEVENT_MSRO | \
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IEVENT_BABT | IEVENT_TXC | IEVENT_TXE | IEVENT_LC \
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| IEVENT_CRL | IEVENT_XFUN)
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#define IMASK_INIT_CLEAR 0x00000000
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#define IMASK_BABR 0x80000000
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#define IMASK_RXC 0x40000000
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#define IMASK_BSY 0x20000000
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#define IMASK_EBERR 0x10000000
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#define IMASK_MSRO 0x04000000
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#define IMASK_GRSC 0x02000000
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#define IMASK_BABT 0x01000000
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#define IMASK_TXC 0x00800000
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#define IMASK_TXEEN 0x00400000
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#define IMASK_TXBEN 0x00200000
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#define IMASK_TXFEN 0x00100000
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#define IMASK_LC 0x00040000
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#define IMASK_CRL 0x00020000
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#define IMASK_XFUN 0x00010000
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#define IMASK_RXB0 0x00008000
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#define IMASK_GTSC 0x00000100
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#define IMASK_RXFEN0 0x00000080
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#define IMASK_RX_DISABLED ~(IMASK_RXFEN0 | IMASK_BSY)
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#define IMASK_DEFAULT (IMASK_TXEEN | IMASK_TXFEN | IMASK_TXBEN | \
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IMASK_RXFEN0 | IMASK_BSY | IMASK_EBERR | IMASK_BABR | \
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IMASK_XFUN | IMASK_RXC | IMASK_BABT)
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/* Attribute fields */
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/* This enables rx snooping for buffers and descriptors */
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#ifdef CONFIG_GFAR_BDSTASH
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#define ATTR_BDSTASH 0x00000800
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#else
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#define ATTR_BDSTASH 0x00000000
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#endif
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#ifdef CONFIG_GFAR_BUFSTASH
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#define ATTR_BUFSTASH 0x00004000
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#define STASH_LENGTH 64
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#else
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#define ATTR_BUFSTASH 0x00000000
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#endif
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#define ATTR_SNOOPING 0x000000c0
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#define ATTR_INIT_SETTINGS (ATTR_SNOOPING \
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| ATTR_BDSTASH | ATTR_BUFSTASH)
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#define ATTRELI_INIT_SETTINGS 0x0
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/* TxBD status field bits */
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#define TXBD_READY 0x8000
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#define TXBD_PADCRC 0x4000
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#define TXBD_WRAP 0x2000
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#define TXBD_INTERRUPT 0x1000
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#define TXBD_LAST 0x0800
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#define TXBD_CRC 0x0400
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#define TXBD_DEF 0x0200
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#define TXBD_HUGEFRAME 0x0080
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#define TXBD_LATECOLLISION 0x0080
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#define TXBD_RETRYLIMIT 0x0040
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#define TXBD_RETRYCOUNTMASK 0x003c
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#define TXBD_UNDERRUN 0x0002
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/* RxBD status field bits */
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#define RXBD_EMPTY 0x8000
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#define RXBD_RO1 0x4000
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#define RXBD_WRAP 0x2000
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#define RXBD_INTERRUPT 0x1000
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#define RXBD_LAST 0x0800
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#define RXBD_FIRST 0x0400
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#define RXBD_MISS 0x0100
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#define RXBD_BROADCAST 0x0080
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#define RXBD_MULTICAST 0x0040
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#define RXBD_LARGE 0x0020
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#define RXBD_NONOCTET 0x0010
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#define RXBD_SHORT 0x0008
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#define RXBD_CRCERR 0x0004
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#define RXBD_OVERRUN 0x0002
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#define RXBD_TRUNCATED 0x0001
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#define RXBD_STATS 0x01ff
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struct txbd8
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{
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u16 status; /* Status Fields */
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u16 length; /* Buffer length */
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u32 bufPtr; /* Buffer Pointer */
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};
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struct rxbd8
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{
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u16 status; /* Status Fields */
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u16 length; /* Buffer Length */
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u32 bufPtr; /* Buffer Pointer */
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};
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struct rmon_mib
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{
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u32 tr64; /* 0x.680 - Transmit and Receive 64-byte Frame Counter */
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u32 tr127; /* 0x.684 - Transmit and Receive 65-127 byte Frame Counter */
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u32 tr255; /* 0x.688 - Transmit and Receive 128-255 byte Frame Counter */
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u32 tr511; /* 0x.68c - Transmit and Receive 256-511 byte Frame Counter */
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u32 tr1k; /* 0x.690 - Transmit and Receive 512-1023 byte Frame Counter */
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u32 trmax; /* 0x.694 - Transmit and Receive 1024-1518 byte Frame Counter */
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u32 trmgv; /* 0x.698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
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u32 rbyt; /* 0x.69c - Receive Byte Counter */
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u32 rpkt; /* 0x.6a0 - Receive Packet Counter */
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u32 rfcs; /* 0x.6a4 - Receive FCS Error Counter */
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u32 rmca; /* 0x.6a8 - Receive Multicast Packet Counter */
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u32 rbca; /* 0x.6ac - Receive Broadcast Packet Counter */
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u32 rxcf; /* 0x.6b0 - Receive Control Frame Packet Counter */
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u32 rxpf; /* 0x.6b4 - Receive Pause Frame Packet Counter */
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u32 rxuo; /* 0x.6b8 - Receive Unknown OP Code Counter */
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u32 raln; /* 0x.6bc - Receive Alignment Error Counter */
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u32 rflr; /* 0x.6c0 - Receive Frame Length Error Counter */
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u32 rcde; /* 0x.6c4 - Receive Code Error Counter */
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u32 rcse; /* 0x.6c8 - Receive Carrier Sense Error Counter */
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u32 rund; /* 0x.6cc - Receive Undersize Packet Counter */
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u32 rovr; /* 0x.6d0 - Receive Oversize Packet Counter */
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u32 rfrg; /* 0x.6d4 - Receive Fragments Counter */
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u32 rjbr; /* 0x.6d8 - Receive Jabber Counter */
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u32 rdrp; /* 0x.6dc - Receive Drop Counter */
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u32 tbyt; /* 0x.6e0 - Transmit Byte Counter Counter */
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u32 tpkt; /* 0x.6e4 - Transmit Packet Counter */
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u32 tmca; /* 0x.6e8 - Transmit Multicast Packet Counter */
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u32 tbca; /* 0x.6ec - Transmit Broadcast Packet Counter */
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u32 txpf; /* 0x.6f0 - Transmit Pause Control Frame Counter */
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u32 tdfr; /* 0x.6f4 - Transmit Deferral Packet Counter */
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u32 tedf; /* 0x.6f8 - Transmit Excessive Deferral Packet Counter */
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u32 tscl; /* 0x.6fc - Transmit Single Collision Packet Counter */
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u32 tmcl; /* 0x.700 - Transmit Multiple Collision Packet Counter */
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u32 tlcl; /* 0x.704 - Transmit Late Collision Packet Counter */
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u32 txcl; /* 0x.708 - Transmit Excessive Collision Packet Counter */
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u32 tncl; /* 0x.70c - Transmit Total Collision Counter */
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u8 res1[4];
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u32 tdrp; /* 0x.714 - Transmit Drop Frame Counter */
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u32 tjbr; /* 0x.718 - Transmit Jabber Frame Counter */
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u32 tfcs; /* 0x.71c - Transmit FCS Error Counter */
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u32 txcf; /* 0x.720 - Transmit Control Frame Counter */
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u32 tovr; /* 0x.724 - Transmit Oversize Frame Counter */
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u32 tund; /* 0x.728 - Transmit Undersize Frame Counter */
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u32 tfrg; /* 0x.72c - Transmit Fragments Frame Counter */
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u32 car1; /* 0x.730 - Carry Register One */
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u32 car2; /* 0x.734 - Carry Register Two */
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u32 cam1; /* 0x.738 - Carry Mask Register One */
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u32 cam2; /* 0x.73c - Carry Mask Register Two */
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};
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struct gfar_extra_stats {
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u64 kernel_dropped;
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u64 rx_large;
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u64 rx_short;
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u64 rx_nonoctet;
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u64 rx_crcerr;
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u64 rx_overrun;
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u64 rx_bsy;
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u64 rx_babr;
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u64 rx_trunc;
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u64 eberr;
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u64 tx_babt;
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u64 tx_underrun;
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u64 rx_skbmissing;
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u64 tx_timeout;
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};
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#define GFAR_RMON_LEN ((sizeof(struct rmon_mib) - 16)/sizeof(u32))
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#define GFAR_EXTRA_STATS_LEN (sizeof(struct gfar_extra_stats)/sizeof(u64))
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/* Number of stats in the stats structure (ignore car and cam regs)*/
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#define GFAR_STATS_LEN (GFAR_RMON_LEN + GFAR_EXTRA_STATS_LEN)
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#define GFAR_INFOSTR_LEN 32
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struct gfar_stats {
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u64 extra[GFAR_EXTRA_STATS_LEN];
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u64 rmon[GFAR_RMON_LEN];
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};
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struct gfar {
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u8 res1[16];
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u32 ievent; /* 0x.010 - Interrupt Event Register */
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u32 imask; /* 0x.014 - Interrupt Mask Register */
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u32 edis; /* 0x.018 - Error Disabled Register */
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u8 res2[4];
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u32 ecntrl; /* 0x.020 - Ethernet Control Register */
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u32 minflr; /* 0x.024 - Minimum Frame Length Register */
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u32 ptv; /* 0x.028 - Pause Time Value Register */
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u32 dmactrl; /* 0x.02c - DMA Control Register */
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u32 tbipa; /* 0x.030 - TBI PHY Address Register */
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u8 res3[88];
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u32 fifo_tx_thr; /* 0x.08c - FIFO transmit threshold register */
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u8 res4[8];
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u32 fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */
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u32 fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */
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u8 res5[96];
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u32 tctrl; /* 0x.100 - Transmit Control Register */
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u32 tstat; /* 0x.104 - Transmit Status Register */
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u8 res6[4];
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u32 tbdlen; /* 0x.10c - Transmit Buffer Descriptor Data Length Register */
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u32 txic; /* 0x.110 - Transmit Interrupt Coalescing Configuration Register */
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u8 res7[16];
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u32 ctbptr; /* 0x.124 - Current Transmit Buffer Descriptor Pointer Register */
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u8 res8[92];
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u32 tbptr; /* 0x.184 - Transmit Buffer Descriptor Pointer Low Register */
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u8 res9[124];
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u32 tbase; /* 0x.204 - Transmit Descriptor Base Address Register */
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u8 res10[168];
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u32 ostbd; /* 0x.2b0 - Out-of-Sequence Transmit Buffer Descriptor Register */
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u32 ostbdp; /* 0x.2b4 - Out-of-Sequence Transmit Data Buffer Pointer Register */
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u8 res11[72];
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u32 rctrl; /* 0x.300 - Receive Control Register */
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u32 rstat; /* 0x.304 - Receive Status Register */
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u8 res12[4];
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u32 rbdlen; /* 0x.30c - RxBD Data Length Register */
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u32 rxic; /* 0x.310 - Receive Interrupt Coalescing Configuration Register */
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u8 res13[16];
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u32 crbptr; /* 0x.324 - Current Receive Buffer Descriptor Pointer */
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u8 res14[24];
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u32 mrblr; /* 0x.340 - Maximum Receive Buffer Length Register */
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u8 res15[64];
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u32 rbptr; /* 0x.384 - Receive Buffer Descriptor Pointer */
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u8 res16[124];
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u32 rbase; /* 0x.404 - Receive Descriptor Base Address */
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u8 res17[248];
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u32 maccfg1; /* 0x.500 - MAC Configuration 1 Register */
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u32 maccfg2; /* 0x.504 - MAC Configuration 2 Register */
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u32 ipgifg; /* 0x.508 - Inter Packet Gap/Inter Frame Gap Register */
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u32 hafdup; /* 0x.50c - Half Duplex Register */
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u32 maxfrm; /* 0x.510 - Maximum Frame Length Register */
|
|
u8 res18[12];
|
|
u32 miimcfg; /* 0x.520 - MII Management Configuration Register */
|
|
u32 miimcom; /* 0x.524 - MII Management Command Register */
|
|
u32 miimadd; /* 0x.528 - MII Management Address Register */
|
|
u32 miimcon; /* 0x.52c - MII Management Control Register */
|
|
u32 miimstat; /* 0x.530 - MII Management Status Register */
|
|
u32 miimind; /* 0x.534 - MII Management Indicator Register */
|
|
u8 res19[4];
|
|
u32 ifstat; /* 0x.53c - Interface Status Register */
|
|
u32 macstnaddr1; /* 0x.540 - Station Address Part 1 Register */
|
|
u32 macstnaddr2; /* 0x.544 - Station Address Part 2 Register */
|
|
u8 res20[312];
|
|
struct rmon_mib rmon;
|
|
u8 res21[192];
|
|
u32 iaddr0; /* 0x.800 - Indivdual address register 0 */
|
|
u32 iaddr1; /* 0x.804 - Indivdual address register 1 */
|
|
u32 iaddr2; /* 0x.808 - Indivdual address register 2 */
|
|
u32 iaddr3; /* 0x.80c - Indivdual address register 3 */
|
|
u32 iaddr4; /* 0x.810 - Indivdual address register 4 */
|
|
u32 iaddr5; /* 0x.814 - Indivdual address register 5 */
|
|
u32 iaddr6; /* 0x.818 - Indivdual address register 6 */
|
|
u32 iaddr7; /* 0x.81c - Indivdual address register 7 */
|
|
u8 res22[96];
|
|
u32 gaddr0; /* 0x.880 - Global address register 0 */
|
|
u32 gaddr1; /* 0x.884 - Global address register 1 */
|
|
u32 gaddr2; /* 0x.888 - Global address register 2 */
|
|
u32 gaddr3; /* 0x.88c - Global address register 3 */
|
|
u32 gaddr4; /* 0x.890 - Global address register 4 */
|
|
u32 gaddr5; /* 0x.894 - Global address register 5 */
|
|
u32 gaddr6; /* 0x.898 - Global address register 6 */
|
|
u32 gaddr7; /* 0x.89c - Global address register 7 */
|
|
u8 res23[856];
|
|
u32 attr; /* 0x.bf8 - Attributes Register */
|
|
u32 attreli; /* 0x.bfc - Attributes Extract Length and Extract Index Register */
|
|
u8 res24[1024];
|
|
|
|
};
|
|
|
|
/* Struct stolen almost completely (and shamelessly) from the FCC enet source
|
|
* (Ok, that's not so true anymore, but there is a family resemblence)
|
|
* The GFAR buffer descriptors track the ring buffers. The rx_bd_base
|
|
* and tx_bd_base always point to the currently available buffer.
|
|
* The dirty_tx tracks the current buffer that is being sent by the
|
|
* controller. The cur_tx and dirty_tx are equal under both completely
|
|
* empty and completely full conditions. The empty/ready indicator in
|
|
* the buffer descriptor determines the actual condition.
|
|
*/
|
|
struct gfar_private {
|
|
/* pointers to arrays of skbuffs for tx and rx */
|
|
struct sk_buff ** tx_skbuff;
|
|
struct sk_buff ** rx_skbuff;
|
|
|
|
/* indices pointing to the next free sbk in skb arrays */
|
|
u16 skb_curtx;
|
|
u16 skb_currx;
|
|
|
|
/* index of the first skb which hasn't been transmitted
|
|
* yet. */
|
|
u16 skb_dirtytx;
|
|
|
|
/* Configuration info for the coalescing features */
|
|
unsigned char txcoalescing;
|
|
unsigned short txcount;
|
|
unsigned short txtime;
|
|
unsigned char rxcoalescing;
|
|
unsigned short rxcount;
|
|
unsigned short rxtime;
|
|
|
|
/* GFAR addresses */
|
|
struct rxbd8 *rx_bd_base; /* Base addresses of Rx and Tx Buffers */
|
|
struct txbd8 *tx_bd_base;
|
|
struct rxbd8 *cur_rx; /* Next free rx ring entry */
|
|
struct txbd8 *cur_tx; /* Next free ring entry */
|
|
struct txbd8 *dirty_tx; /* The Ring entry to be freed. */
|
|
struct gfar *regs; /* Pointer to the GFAR memory mapped Registers */
|
|
struct gfar *phyregs;
|
|
struct work_struct tq;
|
|
struct timer_list phy_info_timer;
|
|
struct net_device_stats stats; /* linux network statistics */
|
|
struct gfar_extra_stats extra_stats;
|
|
spinlock_t lock;
|
|
unsigned int rx_buffer_size;
|
|
unsigned int rx_stash_size;
|
|
unsigned int tx_ring_size;
|
|
unsigned int rx_ring_size;
|
|
wait_queue_head_t rxcleanupq;
|
|
unsigned int rxclean;
|
|
|
|
/* Info structure initialized by board setup code */
|
|
unsigned int interruptTransmit;
|
|
unsigned int interruptReceive;
|
|
unsigned int interruptError;
|
|
struct gianfar_platform_data *einfo;
|
|
|
|
struct gfar_mii_info *mii_info;
|
|
int oldspeed;
|
|
int oldduplex;
|
|
int oldlink;
|
|
};
|
|
|
|
extern inline u32 gfar_read(volatile unsigned *addr)
|
|
{
|
|
u32 val;
|
|
val = in_be32(addr);
|
|
return val;
|
|
}
|
|
|
|
extern inline void gfar_write(volatile unsigned *addr, u32 val)
|
|
{
|
|
out_be32(addr, val);
|
|
}
|
|
|
|
extern struct ethtool_ops *gfar_op_array[];
|
|
|
|
#endif /* __GIANFAR_H */
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