Register slimbus CPU dai link to support slimbus data path.
Change-Id: I3584306ac1e0ad6561a19cecfe71f2a63aadafa9
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
This is done for consistency with other messages printed by this driver.
Change-Id: I373787c8a4f51f0aeba0f0556103707cf256bd43
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
Add support to bump up or down the voltage via sysfs.
# echo 1 > /sys/module/acpuclock_krait/parameters/boost
enables the boost and
# echo 0 > /sys/module/acpuclock_krait/parameters/boost
disables the boost. Boost mode is enabled by default for fast and
nominal devices because those devices could be at the boundaries
of the characterization thresholds and exhibit CPU/L1 errors.
Change-Id: If0dd4ed949188debbb55f82f07004b57548164f6
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
The HFPLL configuration recommended by the hardware designers has been
updated. Update acpuclock to match.
In addition to changes to the static register configuration, runtime
selection of the correct VCO mode is required. For frequencies above
1248MHz, the high-frequency VCO mode is used. The low-frequency mode
is used for frequencies below that.
Change-Id: Ib0585b5262d27791128a54910b75d2dc0c581775
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
Updated hardware recommendations have been released. Capture these.
Although the voltage requirements are higher than was previously
specified, this is not expected to affect actual voltage levels
because the vdd_dig requirements of the of the L2 cache (as
enforced by acpuclock) are already higher than the new HFPLL
requirements.
Change-Id: I4087b35f07276d063d09756067ce7166093f65dc
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
Part of the CPU HFPLL logic lives in the vdd_dig domain and has
voltage requirements that vary based on the PLL frequency. Capture
this in the code.
Even without this change, vdd_dig levels are sufficiently high due
to the vdd_dig votes already made for the L2. This change improves
robustness, however, and protects us should the CPU->L2 frequency
mappings ever change.
Change-Id: Id54a97a5be5dbe4ba61d6fa8ba5b259b3538a0be
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
The current acpuclock-krait driver asserts a constant regulator
current request when a CPU is initialized or inserted, and
removes it when a CPU is hotplug-removed.
Improve on this by allowing the current requests to scale based
on the speed of the CPUs. This allows acpuclock drivers to
factor dynamic power into its current requests, which will
change based on the frequency.
Only msm8974 regulators support current requests, so the cur_ua
column is omitted from the other frequency tables. The 8974
table is populated with pessimistic placeholder currents for now,
until characterization data is available.
Change-Id: I1ef89406a0de0038d32039c361b755a5eedba847
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
Previously, the acpuclock-krait driver changed the rates of these clocks
at boot to match the highest performance levels in acpu_freq_tbl. Instead,
detect and preserve the bootloader configuration until acpuclk_set_rate()
is called. This gets acpuclock-krait out of the business of deciding what
rates the CPUs should be running at, and leaves such policy decisions to
the drivers which call it.
Change-Id: I4feba569c471ca3b08cb5201ab65436503b4455e
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
8930AA support higher cpu frequencies than 8930. Add this
support in this patch.
Change-Id: I6dd40f5f33553c4f13a54df3ed37acf1e32d6546
Signed-off-by: Tianyi Gou <tgou@codeaurora.org>
During rapid open and close of slimbus ports, it may happen that when
port open is performed, the port is not disconnected from the previous
open. This will cause inconsistent state and may result in failure to
playback audio. Fix by waiting for the slimbus port disconnect to happen
before opening the port.
CRs-fixed: 375689
Change-Id: Id1303deae296eb6842074837183ab231aa2b4dad
Signed-off-by: Bhalchandra Gajare <gajare@codeaurora.org>
This patch will queue multiple surfaces and commit those
surfaces into mdp at same instance so that surfaces will
be blended and displayed at same time. Hardware vsync event
is delivered to the user space frame work via uevent. Both
queue and commit are controlled by frame work and synchonized
with vsync event. Therefore frame rate will match with vsync rate.
Change-Id: If630a6d94fd38483ee313f575b1a71ed8bd65a52
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Update mpm bypass list. Add PM8821_SEC_IRQ_N
as the irq controller driver should not be
requesting a wakeup interrupt. This allows
vdd minimization to happen on 8064.
Change-Id: Iabea2219f8d337ae6a7d9821ea9063955781cf74
Signed-off-by: Chandra Ramachandran <cramacha@codeaurora.org>
Add support for CSC and QSEED configuration through MSMFB_OVERLAY_SET and
MSMFB_OVERLAY_PLAY ioctls. Provide better integration than previous attempt
with the existing Overlay and PostProcessing APIs.
CRs-Fixed: 380750
Change-Id: If895391074ef1e7d7a6824d289e1ed9da6a52180
Signed-off-by: Carl Vanderlip <carlv@codeaurora.org>
Remove old implementation of HSIC and QSEED smoothing/sharpening overlay
integration. Need to replace with new implementation that better integrates
the existing functions of the two APIs.
CRs-Fixed: 380750
Change-Id: Id3469fad16764ed88e74a8da75bb873f726ba366
Signed-off-by: Carl Vanderlip <carlv@codeaurora.org>
Signed-off-by: Pravin Tamkhane <pravint@codeaurora.org>
Add support for QSEED Table2 reads/writes. Table 2 is a table of coeffients
for QSEED Table 1 to offset into. Table 2 is quite large, caution should be
taken when writing into it.
CRs-Fixed: 380315
Change-Id: I89be18c0047dcf1d9a3bcd538967b2bbe7b4efe1
Signed-off-by: Carl Vanderlip <carlv@codeaurora.org>
Add support to read the tables of QSEED values. When the values of the
QSEED tables are able to be written to, it is beneficial to be able to read
what's there as well.
CRs-Fixed: 380315
Change-Id: I3110721906424f70a12bf5736de7875dec03f4c6
Signed-off-by: Carl Vanderlip <carlv@codeaurora.org>
MobiCore TZ to HLOS interrupt is assigned a unique SPI.
Currently it shares the SPI with EBI_ERP and moving
forward this interrupt has to be not shared in order
to allow the enablement of EBI_ERP feature..
Change-Id: Ie1895524471f587dd8dbb3a2061b2b7d842d760b
Signed-off-by: Lukas Hänel <lukas.haenel@gi-de.com>
Signed-off-by: Ramesh Masavarapu <rameshm@codeaurora.org>
Some new TSC drivers advertise themselves by using
ABS_MT_POSITION_* bits instead of ABS_*.
This change supports TSC drivers, using
ABS_MT_POSITION_* and/or ABS_* bits.
Change-Id: I1134c0b25cef3d777896ca225b9214929e909d93
Signed-off-by: Baruch Eruchimovitch <baruche@codeaurora.org>
When a free buffer is released/returned back from userspace,
mark it as QUEUED instead of UNUSED. This will ensure that the
buffer is put back into circulation.
Change-Id: Ib6fc058ee2f34044446e777a525f81b2ee971c9c
Signed-off-by: Kiran Kumar H N <hurlisal@codeaurora.org>
Add support for setting up RTB via matching in the device tree
in addition to the platform_data driven model. Also add
the corresponding device for 8974 in the device tree.
Change-Id: I76615fc75ff4fe428cab16a4aa161b032e548983
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Updating diag include file to avoid using mach/msm_hsusb.h which is
deprecated, and update u_bam to include this file as well.
Change-Id: Ia61accc65eb86fe750c3be6dcb0726e480becdae
Signed-off-by: Shimrit Malichi <smalichi@codeaurora.org>
The msm specific parts of ion.h are being moved into a new header
file. For now, add a dummy header file to get clients transitioned
over.
Change-Id: Iac039678e1c3f15d87e67aa667f7e9883ca16669
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Turning off dtv TG may cause blink. MDP requires h/w idle to change
blt mode, turning off TG can make sure mdp h/w is idle. If turning off
TG is not desired, one way to do is to check busy bits of overlay and
dmae and once they are both idle, the mode can be changed.
CRs-Fixed: 363717
Change-Id: I2817d7751ed04fd9ed144974328c4518c54af3d6
Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
To operate correctly, USB core requires to be reset clearing
any initialization settings performed by other components
e.g. bootloader during bootup.
MSM platforms support two kinds of hardware resets:
1. Conventional synchronous reset where clocks to the
blocks must be ON while issuing the reset, and
2. Asynchronous reset which requires clocks to be OFF.
Driver can determine the supported reset methodology on the
platform based on availability of alt_core_clk.
Change-Id: Ia062818ecbf4b0cec44e55f013b762d3ee51b249
Signed-off-by: Manu Gautam <mgautam@codeaurora.org>
Add the master/slave nodes to support bus scaling on 8960 SG
target.
Change-Id: I97e0e04c4f8780d17ec28b6b658bd4919862ab01
Signed-off-by: Gagan Mac <gmac@codeaurora.org>
In AFE-PCM RX and TX dai links of MPQ8064 machine driver there
was a conflict in codec dai name and codec name, with this ALSA
Framework is not creating the node in /dev/snd/
CRs-Fixed: 377509
Change-Id: I5337b216a3d0a2cdc36292ccdafe3e144e7f1d41
Signed-off-by: Santosh Mardi <gsantosh@codeaurora.org>
Some targets require tpiu is disabled before other sinks like ETB
get enabled to get proper ETM trace.
Change-Id: Idcacf7b6515fd17c3a49c74a338258f02631f7cc
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
This allows users to switch between available trace sinks thus
providing user to choose the best switch for the debug use case.
Change-Id: I0c90396010cfcd9f3ab9d3c6d4c1cc7230632c42
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Correct the check for buffer size.
Incorrect check was causing writes to the buffer to fail.
Change-Id: I1c1d757ac9856db60eedecddfaabdd267af954b4
Signed-off-by: Gagan Mac <gmac@codeaurora.org>
This is an initial driver for the new QPIC based NAND controller(NANDc)
that is introduced in MDM9x25. This driver has been leveraged from the
current driver msm_nand.c and is modified for the new hardware changes
in QPIC NANDc. Addition of SPS/BAM support is one of the major
hardware changes in new controller. It also supports only BCH ECC and
based on the device capabilities either 4 bit or 8 bit BCH ECC will
be used. This driver is based on the device tree architecture.
Change-Id: Ie9f782a796bd7c1506997e8eaa1e797310dc26a0
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
This reverts commit 2fed6b6f759ebeb4a678f399a192815c5ab136e5.
Bluetooth sleep mechanism is not stable with the new design.
Change-Id: I9fa7e3af5b2668764f5fb335d93a54451568f857
Signed-off-by: Ram Mohan Korukonda <rkorukon@codeaurora.org>
Add device tree information for NAND controller. Also, add
documentation defining bindings for NAND controller and MTD
flash partition layout for NAND devices.
Change-Id: I6eaf949a54a19aacd3249711033563efd7fd90c2
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
In mmc_wait_for_req_done() function, change the call wait_for_completion()
to wait_for_compltion_io(). This change makes the kernel account for
wait time as I/O wait and through another configuration, this io wait
is treated as busy which makes the acpu clock to scale up.
Change-Id: Iebdc7b1b22871bf845f10a55e2272816c72d9964
Signed-off-by: Murali Palnati <palnatim@codeaurora.org>
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
APPS vote from coldboot may be still pending when SSR is invoked;
so make sure that the APPS votes from coldboot are cancelled before
SSR votes for these Riva regulators.
Change-Id: I975be7470ce08e941c5846642a9379f23574915b
CRs-fixed: 380434
Signed-off-by: Sameer Thalappil <sameert@codeaurora.org>
Use alternate core clocks on the KGSL and Venus IOMMUs,
updating the device tree and clock table accordingly.
Change-Id: Ie201dbe8af37b54c8f479d4788b54010caaea360
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Prop bit is checked in userspace and must be set in driver in order
to be recognized as a direct input device (touchscreen).
Change-Id: I80bf2b9fd390ed58a22a78834f71afe41e3d2776
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
Refactor the IOMMU clock control code to always require a
core clock as well as an interface clock. Add support for
an optional alternate core clock and update device tree
bindings accordingly. Clean up the probe function to remove
needless enabling / disabling of clocks.
Change-Id: I4d744ffabc1e6fb123bacfda324f64408257cb25
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
We see a kernel panic when we reboot with recovery mode
from the UI. Though kernel prepares to stop the other
cores(cpu_relax), but in some race condition mpdecision kicks
in to wake up(CPU_UP_PREPARE) the other core, before we go
ahead for issuing pcom command from core-0 for restart and this
causes a BUG in stop machine code.
So to resolve this before we issue a PCOM_RESET_CHIP command from
core-0, we must ensure that IRQ and FIQ is disabled and also
map the user pages to 1:1 mapping so as to not have unpredictable
MMU errors or kernel panics.
Moving the code put of pm2.c as this code is more restart specific and
not related to power management code.
CRs-Fixed: 359879
Change-Id: If26fdf3a4dd1fb5ecc4c28859bfd68650ff4e747
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Add support for identifying the msm8974 SoC and update the
MIDR fallback table accordingly.
Change-Id: Idc34cac2963776b07ad59c0727bcb49ae42be1ea
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Modify Physical layer settings for PHY strength
and regulator to improve the rise/fall time of
the DSI clock waveform.
CRs-Fixed: 363172
Change-Id: I072fe56a7827ce98222271b6a547154dc337fcef
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Using an unitiliazed spinlock can cause a kernel BUG
in the SMB349 driver.
Fix this by initializing the spinlock in the probe
function.
Change-Id: I9ce691398939f7104b71b58505e2d15dc910328c
Signed-off-by: David Keitel <dkeitel@codeaurora.org>
QSECOM requires a total of 6MB for concurrent
use. The memory is divided between HDCP (3M),
Payready (2M), and QSECOM (1MB).
Increase the QSECOM ION heap from 1MB to 6MB.
Change-Id: I98bef75832e8a774174b1dcd2a18a7d675284ba7
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
The peripheral registrations are stored in a table
on apps processor. During SSR, these need to be deleted
and fresh ones are recorded after SSR completes. Currently
this clean up function is called from interrupt context.
This cleanup function works on a shared table, which is
protected by mutexes. Using this mutex in interrupt function
causes bug with spinlocks and generates warnings. Moving this
cleanup to work queue resolves the issue.
However, there might be race condition with this move. A new
registration might come in, while the clean up is still going on
OR yet to begin. Adding a bit mask which tracks the peripheral
undergoing SSR. if new registration is received from this processor
before clean up is completed, the registration packet is dropped.
Also, an error message is printed in kernel to notify of the drop.
Change-Id: I95e143220a3960d4e9459bb9874bab2911be0937
CRs-Fixed: 371866
Signed-off-by: Shalabh Jain <shalabhj@codeaurora.org>
