Early samples of 8974 v1.0 hardware misconfigure the MPLL1 in
the Modem's primary bootloader. Since this ROM code cannot be
changed, work around the issue by setting a corrected configuration
register value before bringing the modem out of reset.
This change will be reverted when modem support on v1.0 hardware is
dropped, which is expected in the very near future.
Change-Id: Ia422e97730c48b5fd6a6fae084eafd9aa0ee34de
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
(cherry picked from commit ed97e33f4b886f1b5db122a04d6a2ea0238a208c)
(cherry picked from commit 700c500d9e2e1d067c31aa0f2446aea4ffd0c88d)
For convenient debugging of PBL and MBA code, allow the authentication
timeouts to be overridden with a module parameter. With this, the
timeouts can be extended or disabled entirely (by setting them to 0).
Change-Id: I2329a6ee10503b8b7f7d1d0c2fd52fe1aee42e5a
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
(cherry picked from commit d251d8ec509cf22740c55bf98ac4edced1ad4a4d)
LPASS and MSS have different requirements related to the order that
their clocks are enable/disabled and resets are asserted/de-asserted.
Currently, this causes 'clock stuck off' warnings in the kernel logs
when MSS is booted multiple times.
Fix this by reordering the MSS clock calls so that the core_clk reset
is de-asserted prior to enabling its iface_clk. Because doing this
would break LPASS (which requires iface_clk to be on for the core_clk
reset de-assertion to work), we are forced to separate the MSS and
LPASS clock sequences into separate functions and move them into their
respective PIL files.
MSS PIL also requires an additional clock that is added as part of
this fixup. The gcc_mss_q6_bimc_axi_clk is needed for the MSS Q6
to access memory.
Change-Id: Id877781f201a7267f72b52045ed2b87ebf7b4e05
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
Interfacing with some modem subsystem peripherals is not possible
unless the UNCLAMP_ALL bit is set in MSS_CLAMP_IO register. Set
this bit accordingly.
Change-Id: I5685383c506b0bcb89d6b6f808021512079cc607
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
This clock must be enabled for the LPASS Q6 to reach its own clock
registers, so that it can turn on additional clocks on its own. Do
this.
To avoid adding another clock to struct q6v5_data, rename the mem_clk
member in it (used by MSS) to something more generic so it can also
be used by LPASS.
Change-Id: I0b4ec626d249a48dd832a818f630f1f6aed1f98a
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
1.05V is the intended upper-limit for the modem, and is the only
level the peripheral loader driver will need to set. Update this.
Change-Id: I09e14cb2b254688b3e93f61dbea14df62c8fac3c
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
The effects clearing *_RESTART registers are not immediate. A delay
is needed to ensure the subsystem is ready-to-go before registers
within it are manipulated. Fix this.
Change-Id: I12a996a7b5bf34c54a220aae90e8446f94dbdf8c
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
Ensure the write of the image address in the RMB_MBA_IMAGE RMB
register occurs before the writes to the QDSP6SS that releases
the Q6 processor from reset.
Change-Id: I7efbe4e0b81153cc2dc15d8ec60173008478b826
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
