According to the TLMM_v3 hardware spec the INTR_POL_CTL bit
is to be set:
Low for level low interrupts;
High for level high interrupts;
High for all edge interrupts.
Make sure the software configures it as desired.
Change-Id: I3369def7bd00e427c7dfe109bcdd4b6e207ad239
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
The reset state for the INTR_CFG register is 0xE2. We need
the upper nibble to specify the target processor for the
gpio interrupt (Value 0x4 for APPS). But we were ORing
0x4 with 0xE still keeps it as 0xE. Get rid of the
incorrect read, modify, write cycle. Make sure the
reset state is wiped off before setting the interrupt
configuration bits.
Change-Id: I3deee9fcebe9eec78f89635313c5f3d0923fede5
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
With TLMM-V3, the GPIO_INTR_STATUS register now requires
us to write 0 to clear the interrupt status. Earlier TLMM
versions required us to write 1 to clear the interrupt status.
Change-Id: Ic96ab6f3850fd4ac1164761c8f71c88e57fd4de5
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Move enabling the RAW_STATUS_EN at the very beginning.
Hardware team clarified that it is better to write to
RAW_STATUS_EN before writing to any other INTR_CFG bits
in order to prevent spurious interrupts.
Removing writing to the GPIO_INTR_CFG_SU register for
gpio-v2 and remove modifying any other bits except
INTR_ENABLE in mask/unmask calls as it could cause spurious
interrupts as well.
Change-Id: Ia025b324ee3be8073960eac73899f733336cac4c
CRs-Fixed: 346861
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
To unmask a gpio interrupt, the gpio driver sets the
INTR_RAW_STATUS_EN and INTR_ENABLE bits in the INTR_CFG register.
As soon as the INTR_RAW_STATUS_EN is set, the INTR_STATUS is updated
and this causes a spurious interrupt when the irq is enabled.
This is noticed frequently when the gpio is pulled high and requests
a rising edge interrupt or pulled low and is requesting a falling edge
interrupt.
Due the internal circuit design of the TLMM IRQ block, the above method
causes a spurious interrupt when the irq was initialized.
Hence, to avoid this behavior we set the INTR_RAW_STATUS_EN, clear the
INTR_STATUS only once during setup. Every mask and unmask only toggles
the INTR_ENABLE bit.
CRs-Fixed: 346861
Change-Id: I1c9852ed91432582c3d050ccf933053fd368b216
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
In the process we replace the upstream versions of the file with
our own and introduce gpio-msm-v3.c and gpio-msm-common.c.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
