This change adds SPMI Device Tree parsing. The
of_spmi_register_devices() API should be called from the probe()
routine of each SPMI controller to parse the subtree and add the
respective SPMI devices.
The SPMI subtree is nested up to two levels deep. The first level
is the most basic and treats the address as the SPMI slave ID.
This should be used for simple devices that has no notion of
segmented SPMI address spaces.
An optional second level specifies the address as an offset
within the outer layer's slave ID. This is used to specify
multiple devices on the same slave ID that have different address
ranges. In fact, it's reasonable to specify any number of address
ranges at this level.
Devices can also specify any number of interrupts that's decoding
is done by an external interrupt device.
Sections of this code were taken from drivers/of/platform.c.
Change-Id: Ib9f06764a9bd85e3b2aab43b72aa7132885aa044
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
The spidev module is not being removed cleanly since
the SPI device is not being unregistered.
Change-Id: I1f97163b3eef585b420a474cdd2aacc7657e6254
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
Change-Id: I4d5d611a64d8fac4c643e8eb454056ab939eff99
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
Adding a seperate rx buffer for spidev. This allows errors
in transmission to be noticed.
Change-Id: I02258bccf1a4a5543b94c30f51294185498c3c40
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
Adding parameters to spidev module, to allow it to be
added dynamically to the SPI bus. This allows a test
application to insmod it whenever needed and test the
SPI core.
Change-Id: Ifdb7b0c7a67f58d46ebcdc1032f0a654b6c53080
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
Including the following patches:
commit 0f7723bb09440ae69743fed38cf558a838aa9bdf
Author: Bryan Huntsman <bryanh@codeaurora.org>
Date: Thu Oct 6 23:13:56 2011 -0700
Revert "spi_qsd: GPIO configuration changes for SPI chip-select line"
This reverts commit 7eaa08b75995289a91c7dd1f3616f79227f5f923.
Signed-off-by: Bryan Huntsman <bryanh@codeaurora.org>
commit 7eaa08b75995289a91c7dd1f3616f79227f5f923
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Wed Sep 28 16:26:39 2011 -0600
spi_qsd: GPIO configuration changes for SPI chip-select line
The chip-select GPIO's pertaining to each slave remains in suspended
configuration until the first transfer is intiated by the slave.
Change-Id: I3aa8555289be7ce457b91a969cf03909be0965d7
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit e47df9f9b932968152ab2908153e60adab4402d7
Author: Jordan Crouse <jcrouse@codeaurora.org>
Date: Mon Sep 19 11:21:16 2011 -0600
spi_qsd: Fix possible uninitialized variable
Change-Id: Ic0dedbad184046e9835cde015ad5d592f33e82a6
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
commit 4ae02c76b98f2b96bfb8c4fa02f40cfda2f16f97
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Tue Sep 20 17:28:50 2011 -0600
spi_qsd: Fix Klocwork errors in SPI driver
Change-Id: I1fe6632e68ea625966aced37a1b140b30534e101
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit 52e065ba3d86977b59937693ac7e85836cf4eca8
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Thu Sep 1 12:12:58 2011 -0600
spi_qsd: Fix for SPI Operational State Invalid error
This error is reproted randomly when the SPI core is put
into RUN state and occurs when the ACPU clock is low.
When the timer expires, we check again to ensure that the
STATE_VALID bit is set before returning.
Change-Id: Ic8912534f4924efd999b8aa1d75a9fd19749e870
CRs-fixed: 304672
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit a9a8816913e5466e06b443c42cbf8ae866b95fd1
Author: Jeff Ohlstein <johlstei@codeaurora.org>
Date: Fri Sep 2 13:55:16 2011 -0700
msm: dma: remove crci conflict checking
The crci conflict checking code was designed for a system where a crci's
mux could be changed at runtime. In reality, our chips configure these
statically, so it is not necessary.
Change-Id: I4d5f32cd8728d3c78fca8f64aed0e02b57b6afba
Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org>
commit 36c6f1bb48af3e65db281cc7ccb913a8e81a598e
Author: Matt Wagantall <mattw@codeaurora.org>
Date: Wed Aug 17 15:44:58 2011 -0700
msm: clock: Rename all I2C/SPI clocks to 'core_clk' or "iface_clk"
Drivers should now use their device names to distinguish between
clocks of the same type rather than the clock name.
Change-Id: Iab12caf4eab163773d68f1b2adc1bb4c72c69e83
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
commit 55e656e68cac78eaa367341df2e693a483a53f84
Author: Stepan Moskovchenko <stepanm@codeaurora.org>
Date: Mon Jun 6 14:34:38 2011 -0700
drivers: barriers: Replace dsb() with mb()
Replace explicit dsb() calls with mb(). Now that the
generic ARM implementation defines mb() to mean (at least)
dsb(), it is appropriate to switch back to the generic
kernel version of the barriers. This is also needed for
correctness on certain targets (such as 7x27) where dsb()
is insufficient and other operations (such as outer cache
sync or writing to strongly-ordered memory) are required to
ensure proper I/O operations ordering. In some cases,
remove explicit calls to outer_sync following a barrier
since the barrier will now have an explicit outer_sync
call.
Change-Id: I2c53b8534af9c3cbac4d4d77b322f897a39e7758
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
commit 17194a32164b868f80ce84e313f9148d1dc77e7b
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Fri Jun 3 18:10:09 2011 -0600
spi_qsd: GPIO configuration changes
On suspend, the SPI related GPIO's enter a low power configuration
and on resume they move to an active configuration. This helps
conserving power during power collapse.
Change-Id: I0911867e10fadcfc6950f6dddf74226bd6321c16
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit 1777d88688511cd59bad7674c6a2246e0c93142b
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Wed Jun 1 16:54:07 2011 -0600
spi_qsd: Remove restriction on SPI clock speed.
When multiple slaves are connected to the SPI controller,
the driver does not allow the clock to go from lower speed
to a higher speed. This restriction is not required since
there can only be one slave listening at a time. Also,
there are no hardware limitations in doing so.
Change-Id: I4ecabfb3a1515416f050c18678cf0987dcde9d1e
CRs-fixed: 290127
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit 4b7c7bfc546cb02141da9d034421aefe5635f857
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Tue Jun 7 14:18:42 2011 -0600
spi_qsd: Add null pointer check before dereferencing
During probe, there is no cur_msg to set the status.
Change-Id: I82e00b9d74d45c36b70078b171db1bb150d1bfac
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit bf514c766fcc2bdee680f80a2ea16c7fead0be96
Author: Stepan Moskovchenko <stepanm@codeaurora.org>
Date: Mon May 16 13:37:11 2011 -0700
msm: spi: Fix access to unclocked registers
Don't program the GSBI configuration until the clocks have
been turned on.
Change-Id: Idee5f5dffcb5ed0f7de18f1e508ee8c76b618894
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
commit d9c248213f4cd025f3d3586f0de81e4bc44a5a54
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Mon May 16 16:43:08 2011 -0600
spi_qsd: Fix for SPI input overrun error
This error occurs due to a bug in the controller.
This bogus error is reported when a transition from run
to reset state occurs and if the input FIFO has an odd number
of entries.
Change-Id: I555864d4855ac6d416997da69d8bc6aee7a82178
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit e99ceb5b3da7bec51be853809c25df8e32b2c1e6
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Thu Apr 14 18:36:34 2011 -0600
spi_qsd: Multi-transfer handling
When there are mulitple SPI transfers in a message, we
default to using FIFO mode for all the transfers. As special
case, we handle a WR-WR or WR-RD transfer where we choose
between FIFO mode and DM mode based on the total length of
the transaction.
Change-Id: I6fbc1a06a22f9782db5b97c9b87cc53392a8c2fa
CRs-fixed: 276666
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit 8f3d3aaa51603a929027bc820fe2d3515e959779
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Tue Apr 19 14:19:29 2011 -0600
spi_qsd: Ensure IO operation ordering
Adding memory barriers to ensure that the writes and reads
to the SPI and QUP registers happen in the correct order.
Change-Id: I86d8f63b0e9547a2339ee4ab5c713cf8864fef04
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit 36b3fae5f54230cd1e4ca072d1f55cb2f79d8945
Author: Laura Abbott <lauraa@codeaurora.org>
Date: Thu Oct 14 12:48:16 2010 -0700
spi_qsd: Fix section mismatch
The function msm_spi_probe is referenced outside of the __init section.
This fixes the problem by calling platform_driver_probe instead of
platform_driver_register since this device is not hotplugable.
Change-Id: I3a563c6fc562ada959317b54ff60a38f9ce517d8
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
commit dc2e36eecefb6628031afeff28afd9d97f2f3f6f
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Wed Sep 29 16:58:20 2010 -0600
spi_qsd: Changes to support DM mode.
The dma_config function may not always be present.
This change makes sure the driver gets DM resources
irrespective of the dma_config function.
Change-Id: I25a2497d20e973f22b76f2b5d6f68c86bd4d5f1d
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit a39bd4a398674c320925540eec91d94d2b7d53f3
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Thu Aug 19 17:48:01 2010 -0600
spi_qsd: Modify timeout mechanism to check SPI state valid bit.
In order to allow sufficient time for the SPI state
transition to occur, calculate the timeout based on
the SPI clock speed.
Change-Id: I3d6955b2a64a8bf8980590e352fbd564250210fb
CRs-fixed: 250998
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit b5887b644ba9545672d637985713c7e0e2e5bb50
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Tue Aug 3 16:57:33 2010 -0600
spi_qsd: Use FIFO mode when DM mode configuration fails.
When the Data Mover configuration fails, the driver
uses FIFO mode.
Change-Id: Iaf83e50fe725654c58260c5cd1150cdeb56f51c8
CRs-fixed: 249238
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit ced8ad320d480006643a3aa3474f5c0d77457454
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Mon Jun 28 16:01:33 2010 -0600
spi_qsd: Use SW timeout instead of SPI_TIME_OUT register.
Since the software timeout is already present in the driver,
the hardware SPI_TIME_OUT register is being removed.It is just
redundant and used only for debugging purposes.
Change-Id: I829cb944444fc3e5053bc810adffe2b87f511b63
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit 35e9155f59317e8ef63b8ce5190f26f5cae6a8ee
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Fri Jun 25 16:48:25 2010 -0600
spi_qsd: Disable irqs in the probe function.
The irqs are disabled at all times in the probe function
irrespective of the use of remote lock.
Change-Id: I0997d07b93c97a12bca6d80a9bba59682b1bec3e
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit e6af92d74a35ba267125bc61c2c6c18034c03af3
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Tue Jun 22 12:20:46 2010 -0600
spi_qsd: Disable clocks and irqs when SPI bus is not in use.
The SPI clocks and irqs are enabled per workqueue and correspondingly
disabled once the workqueue is completed.
Change-Id: Ib22b7e3b946eb4c829940e43327caaf5aff7721b
CRs-fixed: 242866
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit b25e4220efdacc231cb150fc263af1e3f525b165
Author: Lena Salman <esalman@qualcomm.com>
Date: Tue Jun 8 15:25:47 2010 +0300
spi_qsd: Add usage of MX_WRITE_COUNT register
Use MX_WRITE_COUNT register to reduce the amount of TX interrupts in
FIFO mode for transfers smaller than FIFO size.
Change-Id: I7208fdc85b626a31a8b781ee5c56f73beee6c427
Signed-off-by: Lena Salman <esalman@qualcomm.com>
commit 7ed56f3441c5ebe7fd8107fb8468207a88bc743f
Author: Lena Salman <esalman@qualcomm.com>
Date: Wed Jun 9 16:14:44 2010 +0300
spi_qsd: Minor changes to support Data Mover mode on QUPe core
Minor changes to support Data Mover made on QUPe core.
Change-Id: I54663115a43f7fd9b52a2ddee796b5499d5f239a
Signed-off-by: Lena Salman <esalman@qualcomm.com>
commit a85fd0ab6484eb2ef404c062adffce1ee22337f1
Author: Lena Salman <esalman@qualcomm.com>
Date: Thu Jun 3 13:57:02 2010 +0300
spi_qsd: Add support for QUPe controller
QUPe controller is a new version of Qualcomm SPI controller. The
controller also supports other peripheral protocols, however its SPI
functionality is very similar to previous SPI core, supported by spi_qsd.
Therefore the same driver is being utilized with some register address
modification and minor flow change.
Change-Id: Ic091ef2c2ed699b43f786c278b613e69a7e9039b
Signed-off-by: Lena Salman <esalman@qualcomm.com>
commit ce270f6f9198cf40ee5638b35e595da81116241e
Author: Jeff Ohlstein <johlstei@quicinc.com>
Date: Thu Apr 29 13:40:53 2010 -0700
drivers: spi: Support ADM3 in spi_qsd driver
Change-Id: I6dfa38a4c33a8e4619d56ce30787e1aeafc8356d
Signed-off-by: Jeff Ohlstein <johlstei@quicinc.com>
commit 47346fa611773ef92d12d9145ea33a7f2c79052f
Author: Lena Salman <esalman@qualcomm.com>
Date: Wed Apr 28 11:33:15 2010 +0300
spi_qsd: Add disable/enable of pclk to suspend/resume functions
Add disable/enable of pclk to suspend/resume functions to improve
power performance.
Change-Id: I871e5ac90a998f2942778bb1e8c2c9d583a9ae00
CRs-fixed: 235046
Signed-off-by: Lena Salman <esalman@qualcomm.com>
commit a96eba98fbbd21ac657f5d551466909352766ead
Author: Lena Salman <esalman@qualcomm.com>
Date: Sun Apr 11 10:40:37 2010 +0300
spi_qsd: Making irq code implicit for the core mode in use
Make code clear regarding what mode is in use in the irq.
Signed-off-by: Lena Salman <esalman@qualcomm.com>
commit 6a02d85f8f48cf6f86cddc38c9fce9c1179208b4
Author: Lena Salman <esalman@qualcomm.com>
Date: Tue Apr 13 21:16:45 2010 +0300
spi_qsd: Separate tx/rx/error statistics between contexts
To improve SMP safety, separate the tx/error statistics between
contexts. This protects the statistics from accidentally being
access from another context at the same time.
Change-Id: Ibc52406e7b06a4bb5142f8a09a2f35442cb9df8a
Signed-off-by: Lena Salman <esalman@qualcomm.com>
commit 31f301c171aab8e42f8b6abe9b7866412cb546a8
Author: Lena Salman <esalman@qualcomm.com>
Date: Tue Mar 23 14:51:00 2010 +0200
spi_qsd: Add better handling for pending transfers during suspend
To improve SMP safety, add better handling in suspend function to wait
for graceful closure of pending transfers. This graceful closure waits
for all the pending transfers to finish or timeout, while not allowing new
ones to queue up. This allows correct handling of all the resources
involved in a transfer before suspend.
Signed-off-by: Lena Salman <esalman@qualcomm.com>
commit 8fbf6e4c5371520b5f9de2001e2ebd15773e918b
Author: Lena Salman <esalman@qualcomm.com>
Date: Thu Mar 25 10:44:10 2010 +0200
spi_qsd: Add mutex to get exclusive access to controller registers
To improve SMP safety, add mutex to get exclusive access to controller
registers.
Signed-off-by: Lena Salman <esalman@qualcomm.com>
commit 9405adda67d8c6a856243e599f09d806b4bc6de5
Author: Kenneth Heitke <kheitke@quicinc.com>
Date: Thu Apr 15 16:33:16 2010 -0600
spi_qsd: Move global input_fifo_size to device context.
Fix reference to device data input_fifo_size which is missing from the
previous patch.
Change-Id: Ia469896edd0fd90d7ded2b8ec44f9075474b3ec8
Signed-off-by: Kenneth Heitke <kheitke@quicinc.com>
commit 6031094ca6a940a47437bc6a092e813b4bc41d2a
Author: Lena Salman <esalman@qualcomm.com>
Date: Sun Apr 11 10:34:48 2010 +0300
spi_qsd: Move global input_fifo_size to device context.
To improve SMP safety move global variable input_fifo_size to device
context.
Signed-off-by: Lena Salman <esalman@qualcomm.com>
commit 97f585033413b1f8ae210bbffd617a4af3462982
Author: Lena Salman <esalman@qualcomm.com>
Date: Wed Apr 14 18:35:54 2010 +0300
spi_qsd: Initial contribution of the MSM SPI driver
This adds MSM SPI controller driver. The driver is SPI master, and
allows slave connections. Current version of the driver supports
FIFO and DM modes chosen upon the message size. The driver also
supports loopback mode which can be used for testing purposes.
This is a squashed version of all the MSM SPI driver changes on the QuIC
MSM 2.6.29 kernel which can be found at www.codeaurora.org.
It also contains all relevant adaptations to SPI core changes in 2.6.32
kernel.
https://www.codeaurora.org/gitweb/quic/la/?p=kernel/msm.git;a=blob;f=drivers/spi/spi_qsd.c;h=1c8e3ec727b29040648ef9a4949396f7109528ae;hb=refs/heads/android-msm-2.6.29b
Change-Id: Ibc1e71deb662af87deed77f10dcc8a3a46a8f012
Signed-off-by: Lena Salman <esalman@qualcomm.com>
Signed-off-by: David Brown <davidb@codeaurora.org>
UART clock rate is set to zero while disabling the uart clock for
subsystem restart feature. It is required to set the uart clock rate
to 7372800 Hz while enabling UART clock. Hence use uart_change_pm in
serial core to call msm_hsl_power api to achieve the same.
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
This provides the ability to handle simple debug commands from
an fiq-context uart based debugger.
kmsg - dump printk log
pc - show current PC and mode
regs - show current registers
Other commands are handed off to an IRQ handler which calls the
kernel_debugger() routine provided by KERNEL_DEBUGGER_CORE.
Signed-off-by: Brian Swetland <swetland@google.com>
[ARM] msm_serial_debugger: Better interoperability with shared serial pins.
Introduce debug_enable, debugger will not echo back RX characters until
a CR is received. Other modules can turn off debug_enable via
msm_serial_debug_enable() interface.
Flush when doing TX in FIQ context.
Turn off interrupts and flush when doing TX in IRQ context.
Send a \r with every \n sent by the kernel debugger when processing
console messages.
Signed-off-by: Brian Swetland <swetland@google.com>
[ARM] msm_serial_debugger: irqs command to dump irq count
Signed-off-by: Brian Swetland <swetland@google.com>
[ARM] msm: msm_serial_debugger: Add irq status to 'irqs' fiq debug command.
Also clean up some alignment
Signed-off-by: Nick Pelly <npelly@google.com>
[ARM] msm: fiq_debugger: Add ability to enable / disable debugger at runtime
Signed-off-by: San Mehat <san@android.com>
[ARM] msm_serial_debugger: Support 19.2MHz clock on scorpion.
Signed-off-by: Arve Hjønnevåg <arve@android.com>
[ARM] msm_serial_debugger: Add wakeup irq and disable uart clock when idle
The serial debugger is now inactive by default so we can enter low power
modes. Hit enter twice to activate it for 5 seconds.
Signed-off-by: Arve Hjønnevåg <arve@android.com>
[ARM] msm_serial_debugger: Keep uart clock on when CONFIG_MSM_SERIAL_DEBUGGER_CONSOLE is enabled
Change-Id: I8c4e3c77d429a8f6fde068672d51e750e0f14c1b
Signed-off-by: Arve Hjønnevåg <arve@android.com>
msm_serial_debugger: fix to build without CONFIG_PREEMPT
Change-Id: I71e115a26142cccd809aa979dfa9541f842ae680
[ARM] msm: serial_debugger: move the clock disable to after we enable the fiq
If the uart fifo is not empty when we enable the fiq, the handler will try to
empty it and hang since the clock disabled prior to enabling the fiq.
Signed-off-by: Dima Zavin <dima@android.com>
[ARM] msm_serial_debugger: Add option to keep serial debugger active from boot.
If msm_serial_debugger.no_sleep=1 is added to the kernel command line, or
MSM_SERIAL_DEBUGGER_NO_SLEEP is selected in the config, the serial debugger
is activated on boot and stays active until it receives a sleep command.
Change-Id: Ibf84435af8203360ee808fd903dd6322cf5d9d17
Signed-off-by: Arve Hjønnevåg <arve@android.com>
[ARM] msm_serial_debugger: Fix startup when no_sleep is set
Change-Id: I7e55567d723e30d3e998d625aa7a53f896b55d61
[ARM] msm_serial_debugger: Add option to never disable wakeup IRQ.
This works better if the radio ignores the uart clock request while
power collapsed.
Change-Id: Ib0989e714e883b3667c9ecc4cfd1ebfe014a35df
Signed-off-by: Arve Hjønnevåg <arve@android.com>
[ARM] msm: Fix register dump in fiq debugger
Change-Id: Iff5cd48291c9b09aace30220c4229c157a7db1d0
Signed-off-by: Arve Hjønnevåg <arve@android.com>
[ARM] msm_serial_debugger: Add some debugger commands
Add allregs to dump registers for all modes.
Add bt to get a stackstrace.
Change-Id: Ia85e72b6c8243eba38a04cf4f6cc9cba5342a6de
Signed-off-by: Arve Hjønnevåg <arve@android.com>
Signed-off-by: David Brown <davidb@codeaurora.org>
Fix compilation issues when CONFIG_N_SMUX is undefined and
empty stub functions are getting defined.
Change-Id: I6a9982dac7d9558b8da533f1fc28dddac6c1f8fc
Signed-off-by: Angshuman Sarkar <angshuman@codeaurora.org>
The current design uses the existing channel queues for sending power
commands along with a command filter in the TX worker that always sends
all command messages for queues as long as the TTY UART link is up.
This can allow open and close events to be sent between a request to
power down the link and before the ACK has been received that actually
powers down the link.
Update the implementation to add a dedicated control channel for
power-control commands and bytes. All power commands and bytes are now
sent by the TX worker that properly prioritizes the power commands over
logical channel commands.
CRs-Fixed: 369044
Change-Id: I05c080885c79c3510d02cc360bdfe879d68a962c
Signed-off-by: Eric Holmberg <eholmber@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
Support subsystem restart for SMUX which includes being able to load and
unload the SMUX TTY Line Discipline.
The TTY port is shared between SMUX and memory dump collection which
requires support for gracefully disconnecting after a remote modem
crash and then reconnect after the modem has been rebooted.
CRs-Fixed: 368263
Change-Id: I0fea4c5f0f13c88282f33a7677ac5fd16dc690d9
Signed-off-by: Eric Holmberg <eholmber@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
If a client is unable to allocate a buffer for an incoming packet, the
current software retries once without a delay and then drops the packet.
This causes issues for some clients that use flip buffers for processing
RX data.
This change changes the get_rx_buffer callback failure handling to do an
exponential-backoff retry giving the client time to free up a buffer for
processing.
Change-Id: I3284824a7d5a1d8a03314eebdb4488aaf560440c
Signed-off-by: Eric Holmberg <eholmber@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
Only print power-collapse-enabled message when it is first enabled.
Change-Id: I4b645a0eb345f03762fc1e44eaf953511937db56
Signed-off-by: Eric Holmberg <eholmber@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
To prevent multiple RX operations from overlapping, locking is currently
used during the entire RX operation which also includes calling the
client get_rx_buffer callback in atomic context.
To reduce locking, the RX processing has been moved to a single-threaded
workqueue which ensures serialization of the RX operations. This
minimizes locking requirements and eliminates locking around
get_rx_buffer allowing the client to use GFP_KERNEL instead of
GFP_ATOMIC for memory allocation.
Change-Id: Ib87523191aa77f899fadb7667def58d94579c547
Signed-off-by: Eric Holmberg <eholmber@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
Remove power control bit that is no longer used and is no longer part of
the SMUX protocol.
Change-Id: I727eb7d848d5298c146919f2299a86d17643253f
Signed-off-by: Eric Holmberg <eholmber@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
Unlock spinlock when calling platform_device functions during line
discipline (ldisc) loading an unloading.
This fixes a potential scheduling while atomic condition if the platform
device code needs to allocate memory.
Change-Id: I7dbf15dc62b2276393272392a038c1d846ea2419
Signed-off-by: Eric Holmberg <eholmber@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
For development, the local loopback mode was used. Now that
the full system is ready, disable loopback mode to enable
communication with the remote system.
Change-Id: I24bee29b3fa41690ccbaf8992ecb3cb166dc3ffc
Signed-off-by: Eric Holmberg <eholmber@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
QMUXD from user-space will use this interface to communicate
control plane QMI messages between APPs and QSC modem in Fusion 4.
Change-Id: I2f51f6927a6f92b106548d22c3965575d4468d5a
Signed-off-by: Eric Holmberg <eholmber@codeaurora.org>
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org>
Add new Serial Multiplexer (SMUX) driver.
This driver multiplexes multiple logical channels over a single
physical HSUART channel using the TTY Line Discipline framework.
This driver will be used in Fusion 4 for control plane, data plane
and DIAG traffic between Application processor and QSC modem.
Change-Id: Ibecf6cea872f5baf11fb93ded6124243a37a2085
Signed-off-by: Eric Holmberg <eholmber@codeaurora.org>
Signed-off-by: Angshuman Sarkar <angshuman@codeaurora.org>
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
Create a virtual RTC alarm which restricts max suspend sleep time.
Since the QCT RTC alarm doesn't work properly (yet), we need to clamp the
max suspend sleep time if there is an alarm set for the future. This
ensures that the device will be awake when the virtual RTC alarm needs to
be triggered.
Signed-off-by: San Mehat <san@android.com>
Alarm interrupt causes automatic wakeup even when the phone is in
powerdown state.
Change-Id: If3ae30304adba4f07284a3dc496956d67a1ae1b0
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>
pm8921 chip is equipped with a smart battery gauge called bms.
BMS is capable of intelligently measuring battery parameters
under various loads, the software uses these reading to
accurately determine battery capacity.
Add driver for the bms module.
Change-Id: I0655c19bc9edc6aea15fb66b4de8d647a305416f
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
LTC4088 is high efficiency USB powerpath controller
and Li-Ion/Polymer battery charger. This driver
enables the charger, allows to set current limits,
and detection.
Change-Id: I844431210cfd6e71d02fa7ffb730ee56d8417273
Signed-off-by: Jay Chokshi <jchokshi@codeaurora.org>
Until now only the BMS system was using the ccadc so there was
no need to create a separate ccadc driver.
However we can run in a configuration with BMS disabled
and clients won't be able to read battery current via ccadc.
Separate the ccadc from the bms, this change in is preparation
to add a ccadc api to read the battery current.
Change-Id: Ib96b146d91d01d196df9291eb23432cd430db4d0
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Implement workaround for stuck VCHG.
Some boards do not use the charging feature of the pmic8058 chip. They
however need the software workaround for an issue where the VCHG remains
high even when the USB cable it removed.
Change-Id: Ic92ac0cd913ce88b86706ea013d17789f1acf791
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
The SMB349 charger chip allows charge batteries
with a higher current. Add this driver to be able to
control charging from kernel space and deliver charging
information to userspace.
Also add debugfs entries to show current register
settings of SMB349 charger.
Change-Id: Ic88b539304539a49ebe69517d13045cbb18091bf
Signed-off-by: David Keitel <dkeitel@codeaurora.org>
The smb137b chip from SUMMIT is a Switch Mode charger chip capable
of charging through USB source. It can also provide VBUS when the
system is a host. The driver exposes the charger properties via
the power_supply class. It also interacts with the usb driver for
insertion/removal notifications and charge current information.
The driver also turns off charging and switches to providing VBUS
when told to do so by USB driver.
Change-Id: I0ace31b9e1c7780bc9b40d5a2572340dc97966ac
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
The 8660 FFA has an external smp charger chip from Intersil. Add
the isl9519q charger driver to enable charging from this chip.
Change-Id: I2705c14858f68acc273ed63a0c1e669cb7bc63d9
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
MSM 8660 FFA has two charging paths one via an SMPS charger chip isl9519q
and other via the pmic 8058 chip's linear charger.
Write a driver which talks to the power supply framework and also decides
the optimal charging path depending on the charging cable presence and
battery capacity.
Change-Id: Id00ba526651cb8da688b48b4d1e1d1eb178c1e87
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Rename power_supply_set_charging_by to power_supply_set_online to
more accurately reflect the intent of the API.
Add power_supply_set_charge_type to enable a charger driver to set
a POWER_SUPPLY_PROP_CHARGE_TYPE. Ultimately this is handled like
a request, the receiving charger driver then can handle the request
and report the adequate POWER_SUPPLY_PROP_CHARGE_TYPE once necessary
action has been taken.
Change-Id: Idf4760c7d6c0f61a9eccc656cd469a6ac5fdc6cd
Signed-off-by: David Keitel <dkeitel@codeaurora.org>
Add two APIs, 1) set_current_limit API and 2) set_charging_by.
set_current_limit api is used for external control, such as for USB
driver to tell a charger driver the maximum current to draw.
set_charging_by is used to change the state of the charger.
Change-Id: I147eab37836b54627ca1458167eb117ba3eacd7a
Signed-off-by: Willie Ruan <wruan@codeaurora.org>
USB BAM driver to support BAM-to-BAM
USB<->Peripheral transactions.
Change-Id: Ib49a41f5dcdccb6f6bff2492fa64ead40f18b870
Signed-off-by: Ofir Cohen <ofirc@codeaurora.org>
The driver controls the SPS hardware DMA to move data in the following
modes:
1. Peripheral-to-Peripheral
2. Peripheral-to-Memory
3. Memory-to-Memory
This driver complies to BAM hardware version#2.
Change-Id: I1b2b503893cf6891b47201da0f44a47ce7511ece
Signed-off-by: Amir Samuelov <amirs@codeaurora.org>
Signed-off-by: Kenneth Heitke <kheitke@codeaurora.org>
SSBI is the Qualcomm single-wire serial bus interface used to connect
the MSM devices to the PMIC and other devices.
Since SSBI only supports a single slave, the driver gets the name of the
slave device passed in from the board file through the master device's
platform data.
SSBI registers pretty early (postcore), so that the PMIC can come up
before the board init. This is useful if the board init requires the
use of gpios that are connected through the PMIC.
Based on a patch by Dima Zavin <dima@android.com> that can be found at:
http://android.git.kernel.org/?p=kernel/msm.git;a=commitdiff;h=eb060bac4
This patch adds PMIC Arbiter support for the MSM8660. The PMIC Arbiter
is a hardware wrapper around the SSBI 2.0 controller that is designed to
overcome concurrency issues and security limitations. A controller_type
field is added to the platform data to specify the type of the SSBI
controller (1.0, 2.0, or PMIC Arbiter).
Change-Id: Ic37e1505f0ed7cfb8c5926a4c8d1770aa43e67cc
Signed-off-by: Kenneth Heitke <kheitke@codeaurora.org>
This is the initial version of the Wireless ConNectivity SubSystem (WCNSS)
WLAN driver. The WCNSS is a new Hardware integrating WLAN, BT and FM
technologies that is built into new MSM chip. This version of the driver
does basic WLAN device detection, WLAN SMD channel allocation probing and
trigger the PIL to download the WCNSS SW image.
Change-Id: I054566453152e8d8d02f79693e6a51f26d047835
Acked-by: Jeff Johnson <jjohnson@qualcomm.com>
Signed-off-by: Yunsen Wang <yunsenw@codeaurora.org>
