For cmd mode the frame rate calculation result is wrong. Also in mdp
driver there are several places to do the same calculation. So fix the
wrong calculation and use a single func to do calculation.
Conflicts:
drivers/video/msm/msm_fb.c
Change-Id: I3a4be39e480ce82677dcefb666202947f7f6d3c1
Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>
(cherry picked from commit d4eb5a1a3ef0935ce6aeffb2b48974c01b9518b9)
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
The mapping for several RPM resources for the MSM8930+PM8038
target is incorrect. Add and update enum values in order to fix
the mapping.
Without this fix, requests made for the following resources will
appear as 0 when received by the RPM processor: NCP, CXO_BUFFERS,
USB_OTG_SWITCH, HDMI_SWITCH, QDSS_CLK, and VOLTAGE_CORNER.
The incorrect VOLTAGE_CORNER mapping results in the VDD_CX
regulator always staying at a low voltage even when the clock
drivers have requested a high voltage immediately before scaling
up the Krait core frequency. This could lead to stability issues
during high load use cases.
Change-Id: I9efcf8185f9f3a017760c72baa3b8fdb213c770a
CRs-Fixed: 426912
Signed-off-by: David Collins <collinsd@codeaurora.org>
(cherry picked from commit b0e5b25377efe354f39860daf0591f340b0108dc)
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
Serial core allocates circular buffer for uart tx transfer.
Circular buffer head and tail is updated in serial core and
circular buffer tail is updated in uart driver.While uart
transfer is happening, uart client bluetooth hci_ldisc,calls
uart_flush_buffer in serial core and sets circular buffer
head and tail to zero.As uart driver does not know when
uart_flush_buffer is called in serial core by uart client,it
updates circular buffer tail for the previous ADM Tx completion.
This leads to queueing Tx command to ADM although no data is
there in circular buffer.Because of this,uart client is not
functional.
Hence adding msm_hs_flush_buffer api which notifies to uart driver
that uart_flush_buffer is called in serial core by uart client and
set tty_flush_receive flag to true.In uart interrupt handler ,do
not update circular buffer tail if uart_flush_buffer is already
called in serial core by uart client else update circular buffer
tail on ADM Tx completion.
(cherry picked from commit ce39410ad3db5b9fb446bf5da126585d58fa872a)
Change-Id: I9bce30da218f42739c175d9b3c283ae39b6b5c89
CRs-Fixed: 419054
Signed-off-by: Saket Saurabh <ssaurabh@codeaurora.org>
New characterization data shows that vdd_dig voltage for L2@384MHz
can be lowered to the low level. Update the data in this patch.
Change-Id: I7258c54a7245082cfd0d186d32fe7ab792cc8874
Signed-off-by: Tianyi Gou <tgou@codeaurora.org>
(cherry picked from commit 60f828d94cf249a5216512eedfc679ebf2fe18cf)
-Non tunnel playback is use case where compressed
data is sent to driver(for decoding) and
caller expects PCM data back from the driver.
-Add non-tunnel driver for amr-wb+.
-Add support for amr-wb+ in asm driver
Change-Id: I266e70dff0466a20b0435da840a31a8a1774cf35
Signed-off-by: Ajit Khare <ajitk@codeaurora.org>
mdp bus client could be registered multiple times without the check.
Change-Id: I582741c75e815873357e62bc9bf0ff61a4cecf9f
Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>
Always mark GPU contexts that have cause a GPU hang as guilty.
If the GPU context recovered successfully, still mark it as guilty.
This will inform applications that something might have
gone wrong and to take actions to ensure everything is correct.
Also, swap out any active context following a hang. This will
ensure that any new submissions will force the context to be restored
before it is used.
CRs-fixed: 427603
CRs-fixed: 405434
Change-Id: I6b7cf2b2a680a4691f45535a147ca678a4d961f3
Signed-off-by: Carter Cooper <ccooper@codeaurora.org>
Add SFAB voting in QSEECOM_IOCTL_PERF_ENABLE_REQ.
The SFAB clock needs to be bumped up to its optimal
value when opearting in high bandwidth mode (for max
crypto performance)
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
(cherry picked from commit 8e2d73a0ade94ffd27882043d562c7ee825d9f7c)
Conflicts:
drivers/misc/qseecom.c
Change-Id: I281e544756304f19969afbab7196a227dad0e2b1
Signed-off-by: Sudhir Sharma <sudsha@codeaurora.org>
In the current functionality, if DFAB clock is already on and a
request is made to turn on SFPB clock, the DFAB clock is turned
off and SFPB clock is turned on and vice-versa.
The above situation can lead to unexpected errors. The current fix
makes sure that clocks that are on are not voted to be off without
explicit request.
Change-Id: I6c3230e23b105c049cdb0aace579b8a176328c84
Signed-off-by: Ramesh Masavarapu <rameshm@codeaurora.org>
(cherry picked from commit 8d7565828aca6023ca968d2e5350737bd6d86215)
Bring the msm8960-perf_defconfig and msm8960_defconfig in alignment by
making sure they have the same WLAN configuration.
CRs-Fixed: 440816
Change-Id: I673a23a7d4d1646bb6bec8a1bf794ed6819717d0
Signed-off-by: Jeff Johnson <jjohnson@codeaurora.org>
Previously, a parameter was added to secure heaps to only
allow secure allocations. Some clients still require
non-secure contiguous allocations even though the SMMU is
supported. Add support for those clients to force contiguous
allocations to go through.
Change-Id: I0d18d8a9ed3ab267b55c84c4ad160f8cec2c2b32
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
The GPIO mux config varies with the platform. Hence add support
for correct camera GPIO mux corresponding to SGLTE platform.
Change-Id: I7fe745013c813fd079852e2f04ae23d3f021533a
Signed-off-by: Rajakumar Govindaram <rajakuma@codeaurora.org>
When the cmd sent by HAL is notified to the daemon, copy the
result of the processing of that ctrl command like status, back
to the userspace.
Change-Id: I6209981fb18abd7d4bd55e1f6525998f7fa14ddf
CRs-Fixed: 411688
Signed-off-by: Kiran Kumar H N <hurlisal@codeaurora.org>
This change adds free buffer api to video
client's flushing state to allow buffer
freeing in flush state.
CRs-fixed: 430214
Change-Id: I970efbbd8cc503eab4b944e12630f1b1faa9069c
Signed-off-by: Maheshwar Ajja <majja@codeaurora.org>
Add the SoC ID and cpu_is wrapper for identifying the
APQ8064AA SoC.
Change-Id: Ia038088045e1170fe897f8ba0a9ab725e5acab20
Signed-off-by: Jay Chokshi <jchokshi@codeaurora.org>
(cherry picked from commit 38ccbee9a1f823640542f1e9d73a041d18337b2e)
Conflicts:
arch/arm/mach-msm/socinfo.c
Signed-off-by: Shruthi Krishna <skrish@codeaurora.org>
Currently CPUs that have entered nohz idle mode are not being woken
up to perform load balancing. Turning on SCHED_MC will fix that, and
will also cause CPUs to show up at the correct level of scheduling
domain (MC).
SCHED_MC would normally also cause SD_SHARE_PACKAGE_RESOURCES to be
turned on at the MC level as well, causing a task to be migrated to
an idle CPU when the task is woken up. Previous modifications to
SD_SHARE_PACKAGE_RESOURCES however have restricted its effect
to tasks that have the PF_WAKE_ON_IDLE flag set.
Certain target configurations (msm7627a*, msm8660*) are being left
out until they are verified with SCHED_MC.
Signed-off-by: Steve Muckle <smuckle@codeaurora.org>
Conflicts:
arch/arm/configs/mako_defconfig
arch/arm/configs/msm8910_defconfig
Change-Id: I1c8a311e724cedfebe6997e48ddebf837c14e7a1
AVS fine tunes the processor core voltage based on the current
system conditions and process technology.
Change-Id: Ia44acfa82bf921632d66576f9028bb4abfe976b5
Signed-off-by: Praveen Chidambaram <pchidamb@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Anji Jonnala <anjir@codeaurora.org>
Enable avs(bit 27 in SAW2_AVS_CTL) by default
in the board file which can be usefull later to
avoid unneccesarry enable/disables(for avs unsupported
targets).
CRs-fixed: 423827
Change-Id: I2ec49078e2811b8e515260d66462f8ee2ff4e38b
Signed-off-by: Anji Jonnala <anjir@codeaurora.org>
Do not enable/disable AVS on targets where it is not enabled at boot.
Enabling it on targets when AVS isn't enabled and the AVS control
parameters aren't configured, causes undefined behavior and random
crashes.
Change-Id: Id0c4e10618437eed1b383145a6a4f25bbd901647
Signed-off-by: Anji Jonnala <anjir@codeaurora.org>
Changing the voltage with the AVS feature enabled requires
certain care. First, temporarily disable AVS before writing any
registers which would change the voltage. Then kick the PMIC
state machine back to the idle state so that our write to the
VCTL register takes effect immediately. We don't need to check
the state machine for idle, instead we should just confirm that
the SPM has sent the voltage we wanted to send and then we can
program AVS to allow up to 4 12.5mV steps down from the voltage
programmed in VCTL. Once this is all done reenable AVS so that
the voltage can be decreased after the AVS_DELAY counts down.
Change-Id: I1c23fd0549e401152fd16de9032ceaf7c3e067c4
Signed-off-by: Praveen Chidambaram <pchidamb@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Anji Jonnala <anjir@codeaurora.org>
* This defconfig is based off msm8960-perf_defconfig
* Enable WLAN in kernel driver configs
Change-Id: Id6beb88349d00e7631344725ff35e9bfd959cf75
Signed-off-by: Ajay Dudani <adudani@codeaurora.org>
Memory allocated for "buf_entry" and "sched_cctxt"
is not freed in case if error is returned. This
change prevents possible memory leak in video
decoder driver.
CRs-fixed: 432323
Change-Id: I1c8775fb701f1568f704b6ddbb4e835304d2a817
Signed-off-by: Shobhit Pandey <cshopan@codeaurora.org>
This patch allow satge commit without pipes queued to
allow a pipe to be un-staged from mixer immediately after
overlay_unset.
Change-Id: I03abb907c66cce3d0559743d3bb1eb26a88dc78a
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>
Sensor regulator could be still invalid at the time of a system
suspend, this change is to avoid freeing NULL regulators under such
occasion.
Change-Id: Ia520b2516b43feaa3fbbbe30628cc47ee7fad96a
Signed-off-by: Wentao Xu <wentaox@codeaurora.org>
This reverts commit 355c0ffe69b90b08ec4621bdb0964b42c6bb7eed.
Reverting it, as this is being handled in Display HAL now.
Change-Id: I2d807a17193c8d579bb23378e59817374d3f4ad7
Signed-off-by: Sushil Chauhan <sushilchauhan@codeaurora.org>
Add reference counting to all KGSL events since they are dependent
on the context. This avoids a race condition where the context
could be destroyed while the events are being processed during cleanup.
CRs-fixed: 438134
Change-Id: Ic2cd484d441e4c392ab63b0a0131accaceafc711
Signed-off-by: Carter Cooper <ccooper@codeaurora.org>
Cpufreq suspend variable get's updated in kernel pm notifier
callback which gets called in process context. This will create
window where cpufreq governor may try to change the frequency
before suspend variable is updated while resume.
Define suspend/resume for cpufreq driver to update suspend variable
in atomic context.
Don't update the policy->cur upon cpufreq driver failure.
CRs-fixed: 423791
Change-Id: Id78705f5c3b8bf801c6253e9362299280903769f
Signed-off-by: Anji Jonnala <anjir@codeaurora.org>
Add platform device for PC debug counters. These counter stores the
warmboot entry/exit counters for each core on a non-cacheable always
on IMEM memory. This is a useful feature during debug to understand if
the system has correctly warmbooted after a power collapse.
Usage for core0 debug counters:-
counters at address 0x2A03F664 represent no of times PC attempted.
counters at address 0x2A03F66C represent no of times PC failed.
counters at address 0x2A03F668 represent no of times warm boot happened.
no of PC attemps = PC failures + warm boot entries.
Change-Id: I3f78921f1ddd55967284fb7839a98bdb43efbeb9
Signed-off-by: Anji Jonnala <anjir@codeaurora.org>
The power collapse entry counters are incremented after the caches are
flushed during power collapse. In order for the counters to reflect the
current values, in the event of a crash, the counters have to be in a
non-cacheable memory.
Change-Id: If24a41cfa630fe0e843a4d41949ff38e1412889d
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
Add warmboot entry/exit counters for each core on a non-cacheable always
on IMEM memory. This is a useful feature during debug to understand if
the system has correctly warmbooted after a power collapse. The debug
counters start at a memory offset of 0x664 on the IMEM. Each core
reserves 4 words for events, of which 3 are being used to monitor the
following events,
1) power collapse entry
2) warmboot exit
3) failed power collapse when wfi returns with a pending interrupt.
Change-Id: I45aac8e4a4d3421d586790b3b66fd71a8d88ea9d
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
Add SPM sequences to do Krait retention for 8960,8930
and 8064. Also added a new rpmrs level containing the
latencies and power measurements for this new low power
state.
CRs-Fixed: 369864
Change-Id: I321fa22ab891b929366444f6187876c57f87c421
Signed-off-by: Anji Jonnala <anjir@codeaurora.org>
An incorrect ordering in the check of allowed modes, results in
standalone power collapse not getting selected when the secondary
cores are online.
Change-Id: Idc7177b78bd0ce7563cc27afbf6c12d3bc1f9f9a
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
To prevent the Krait core configuration from being indvertently changed
when doing L2 power collapse, save a few CP15 registers and restore them
back after coming out of power collapse. This needs to be done after
switching the Krait from active freq to QSB clock source.
Before doing power collapse, the core0 clock switches over to QSB. However,
QSB can run at any frequency and the voltage required for that
frequency, needs to be ensured when coming out power collapse. If the
QSB clock at resume, is a higher frequency at than the QSB clock was at
collapse, then we may run the risk of running at higher clock with a
lower voltage.
Hence, switch to 1.0 V (safe vdd) when going into PC (after switching to
QSB clock source) and the SPM would resume at 1.0V. After the core
starts running, restore the CP15 registers and switch to the previously
saved active voltage, before switching clocks to the active frequency.
This is applicable only for APQ8064.
Change-Id: I75a70f5e07bd581fc8028bed79de7ee796f4c411
Signed-off-by: Praveen Chidambaram <pchidamb@codeaurora.org>
Resetting SDCC-BAM after reset of SDCC-DML causes
interface disconnect between SDCC-BAM and SDCC-DML
and lead to hang when SDCC driver initiates data
transfer in BAM mode. Modify the SDCC reset sequence
to reset SDCC-DML after reset of SDCC-BAM.
CRs-Fixed: 423399
Change-Id: Ia31d40e30cbf95befba3b1133a525a81903789f2
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
(cherry picked from commit b745eeb229a476d81ee4177adfe168d3a35bda47)
Add virtual ANC widgets which are used to enable ANC
before PA is turned on, and to disable ANC before TX is
turned off.
CRs-fixed: 387904
Change-Id: I8c2fa670062f1486499c79653a2c223f7daba84f
Signed-off-by: Damir Didjusto <damird@codeaurora.org>
Moving RGB1 and RGB2 to AXI port 1. This fixes underrun issues seen
on External display while connecting and disconnecting HDMI. This patch
evenly balancing pipe loads on each port.
Change-Id: I2dc1166d04bb938f9e233a6de52f1a8a3fdd29e2
CRs-Fixed: 435458
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>
During error cases, there might be situation, when slimbus channels
are being closed even when the number of active channels for
that DAI is 0. Avoid decrementing ch_act field if it is already 0.
Change-Id: Ie988eb049a20fc7cf5725ddc183ee1ae5fcb758d
Signed-off-by: Banajit Goswami <bgoswa@codeaurora.org>
If init call for LED flash is missed / failed, gpio_request() may not
be performed for gpio pins for LED flash. This causes stability issues
where gpio calls are performed without gpio_request. Check for valid
client before performing gpio configuration.
Change-Id: Ib232dd53b52af06981d53c799b000ac7f4917c9d
Signed-off-by: Sreesudhan Ramakrish Ramkumar <srramku@codeaurora.org>
(cherry picked from commit 952001729813a0184d95e20f30bee89d6a4cd9bc)
Characterization data shows that L2 runs up to 667MHz with vdd_cx at 1.05v.
Therefore, update the L2 voltage table to match the new data.
In addition, update acpuclock table to use the updated max L2 frequency
with vdd_cx at 1.05v.
Change-Id: I05ce13b9050a4b084d10a8f15dfa3bfe40d5fbe5
Signed-off-by: Tianyi Gou <tgou@codeaurora.org>
(cherry picked from commit 222732641a6b3a7eb81244c994c7d88435bedb45)
Signed-off-by: Dhivya Subramanian <dthiru@codeaurora.org>
To avoid a core vdd being set when the core could be executing the SPM
finite state machine, set the call to set vdd to execute on that
particular core using smp_call_function_single(). However, the call can
only be executed on a core thats online.
When a core is brought online, the acpuclk driver needs to ensure that
the core vdd is set correctly before the core can be brought online.
But, since smp_call_function_single() works on cores that are online,
the call to set vdd will fail and therefore the core will cannot be
onlined.
The error that would be seen when the kernel command line parameters has
maxcpus=2
[244.759529] saw_set_voltage: 8821_s0: msm_spm_set_vdd failed -6
[244.764687] acpuclk-8064 acpuclk-8064: regulator_set_voltage(krait2)(-6)
[244.771463] _cpu_up: attempt to bring up CPU 2 failed
It is safe to do a set the vdd of an offline core when called at cpu_up,
so bypass smp_call_function_single() and set the voltage of the core
directly from cpu0.
This chicken and egg problem will not be seen if the cores were
initialized by calling boot_secondary() at init.
CRs-fixed: 407553
Change-Id: Ifdc9a645b5a9715d0fda065b4b0c2bab056a3ade
Signed-off-by: Praveen Chidambaram <pchidamb@codeaurora.org>
(cherry picked from commit 8624ce7c52bba5acf7a2321690def8c732680199)
Signed-off-by: Dhivya Subramanian <dthiru@codeaurora.org>
Some CPU designs may be able to recover from certain types
of L1 instruction cache errors. Rather than panicing
whenever any kind of L1 error is encountered, add an option
to selectively panic on recoverable L1 errors.
Change-Id: Id8beb0e58d41fa5319f4ca76c5f35e2162f8b704
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
(cherry picked from commit e1aba3d9b510d34e8309669d811a6f01568858dc)
Signed-off-by: Dhivya Subramanian <dthiru@codeaurora.org>
mdp_clk_ctrl on is not called when commit is from overlay commit path
which can cause mdp hang. mdp_clk_ctrl off should be after mdp
overlay2 is done, so schedule a work in overlay2 done isr.
Change-Id: I94fd08da27cfda114f5cc0056a5103f0a9b772f6
Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>
Change the sleep-set force mode configuration for MSM8930 PM8038
SMPS 3 from LPM to AUTO. This modification ensures that the
modem processor does not crash in use cases where it is active
and heavily loaded while the Apps processor is asleep.
Change-Id: Id04feb4a0a07b4d27bcdc1f89dd9ffd24acb42d7
CRs-Fixed: 421559
Signed-off-by: David Collins <collinsd@codeaurora.org>
-While music playback is done and PCM close sequence
is in progress, if headset is inserted this will report
headset insert to snd_soc_jack_report. But it will get
stuck here waiting for lock that is already acquired by
DAPM at PCM stream close snd_soc_dapm_stream_event.
-Change the function call used to report insert/removal
from snd_soc_jack_report to snd_soc_jack_report_no_dapm
that fixes this deadlock.
CRs-Fixed: 429766
Change-Id: I167e45bdce9790ff7e878528629c4d652029bf26
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
FIR and M/N scalar when used for downscaling, drops
alpha channel of the given layer. To notify this, alpha_drop flag
is updated accordingly. This flag need not be checked for layers
with no alpha plane. In some scenarios alpha_drop may get enabled
for the layers with no alpha plane and cause issues realted to blend
composition of layers. Check for setting alpha_drop only if source
ayer has alpha plane.
Change-Id: Ie64b30c045a78d0d68eb9efacc76902afae7850d
Signed-off-by: Mayank Chopra <makchopra@codeaurora.org>
This reverts commit 181fc587a179363624b9a3b47bcd0c04c05a8553
Reverting as Bluez stack need to be supported
Change-Id: Iea6169f19bc47786879845d1318ec47538ec1b1d
Signed-off-by: Bhasker Neti <bneti@codeaurora.org>
