When setting the NSCFG field, the S2CR register being
written needs to be indexed by the stream matching group,
not by the value of the SID being configured. Additionally,
there is no need to set CBACR for every SMR that is
programmed.
Change-Id: Ib79771a3bd87e4bd3b353bd5c6de9247138ca43e
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
(cherry picked from commit c51f77cf28c2deba250444b51e88d87339890915)
Signed-off-by: Sudhir Sharma <sudsha@codeaurora.org>
(cherry picked from commit b8cda0f34f2fc7369dddd833e41edcdbe75642c2)
Refactor the IOMMU clock control code to always require a
core clock as well as an interface clock. Add support for
an optional alternate core clock and update device tree
bindings accordingly. Clean up the probe function to remove
needless enabling / disabling of clocks.
Change-Id: I4d744ffabc1e6fb123bacfda324f64408257cb25
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
The hardware requires a TLB sync operation at the end of
each TLB maintenance operation.
Change-Id: I8102253cfc12af530216346efa5bb9760db25352
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Query SMT and SID mapping information at probe-time instead
of attach-time to allow this information to be
error-checked at an earlier time.
Change-Id: Ib2bbdc8374f9c86c3e6013d298fe8b279b53d83b
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Since the IOMMU ID registers are only accessible by the
secure environment, specify the SMT sizes in device tree
so that the IOMMU driver knows how many SMRs to initialize.
Change-Id: I614a51069c0304f71b0c7d061d97aca0289c17ea
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
The IOMMU hardware blocks are power-gated by GDSCs which
need to be enabled prior to programming the IOMMU hardware.
Change-Id: I5b4e5a0a60ce672c1180faaf3a8344d72a6ebe5e
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Enable and disable the IOMMU clocks for each high-level
mapping operation rather than leaving the clocks enabled
between attach-time and detach-time even if no IOMMU
operations are being done.
Change-Id: I4cde881992b8cd77fb4ea7e8dc1c003f639d15b6
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
SMMU global address space programming need to be performed
each time the device comes out of power collapse, move the
programming of global address space from driver initialization
to the point where the attach is initiated by the clients.
When the first context is attached, the global address space
is programmed prior to the programming the context.
Change-Id: I36e4f161861823aa43d15c3271f8d9b26214cb84
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
SMMU v2 is based off the ARM SMMU architecture specification.
The SMMUs primary purpose is to provide virtual address translation
and abstract the physical view of system memory. In doing so,
discontiguous physical memory appears virtually contiguous to
hardware cores.
The SMMU instances are now represented in device tree with each
instance having multiple translation context banks.
Change-Id: If4733500e5226984d26f1c8a97ae98603c2f75f9
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
