Remove using hardcoded value for the TMC ETR allocation size in
the TMC driver and instead get the size from the DT node. This
will ensure only one location (DT) controls the size of the
allocation.
Change-Id: I642d149e124c98470821ac4a37627747aecd2af7
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Dump TMC ETF and TMC ETR registers on abort to allow post crash
parsing. Also ensure magic value is written for TMC ETF buffer
dump.
Change-Id: I8f21c456bcc79ed3e2831bd6bd1e6a6dbfdb93d0
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
MSM9625 implements ETM based on ETM version 3.5.
As such the 9625 ETM registers need some additonal configuration
for ETM to be functional. They also have some extra registers which
need to be configured properly while some registers currently being
configured by the driver are absent on 9625. Additonally, the ETMv3.5
can be configured to support data tracing, support for which is
not present in the existing ETM driver.
Change-Id: Ic3e61d0d1abf371653a398a28111b308747a7b6f
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
When PC save is enabled via kernel command line or config item
but we boot with maxcpus parameter value of less than number of
present cpus, cpus that are not included as part of maxcpus don't
get PC save feature enabled during kernel init since those cpus
would not be online.
This change ensures that for such cpus, first hotplug after the
respective cpu's ETM probe is done, enables PC save feature if
the feature is enabled via kernel command line or config item but
hasn't already been enabled.
Change-Id: I9cae33654539ed72885fdf11cd603c7c776512c1
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Having both both ETMPDCR[3] set and ETMCR[0] cleared causes
pre-mature resumes from suspend power collapse. For now, clear
pwrup (ETMPDCR[3]) right after clearing pwrdwn (ETMCR[0]) to
avoid pre-mature resume from suspend power collapse.
Change-Id: I4b951ecc672d42aa9ea1feb7a5f999d24698405e
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Consistent with the what is done for TMC ETR, keep the
drvdata->size as representing the size of the actual buffer for
TMC ETF as well since size is used while dumping the buffer.
Change-Id: I2b5355a822898804add81c92bdd2992343195f2c
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Send data over STM only if the data length specified is non-zero.
This will avoid potential issues while avoiding sending empty
packets.
Change-Id: I1792d4b342bdb8cae2c0a8edc2d2584b42c72f6f
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Add support to transport data sent using userspace library over
STM. Data stream will contain the entity id, protocol id and
options.
Change-Id: I5bd1810338fd13373bbad7de559765002c43c500
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Fail ETM enable if the core is offline so that it is obvious to
the user that the operation failed. ETM disable cannot fail so
disable ETM during hotplugg off if it is user enabled and
re-enable ETM during hotplugg on if it is user enabled.
Change-Id: I24120582ff6d3c5f3598baff962dc2ef910c3a1e
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Switch to using spinlocks instead of mutexes to make apis
callable from atomic context.
Change-Id: I6c249b66c7f9db3d6028f1ab92bacfbcf43b150e
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Fail pcsave enable/disable if the core is offline so that it is
obvious to the user that the operation failed.
Change-Id: I2bd88636e1982a7de6b14f8b742d1f9bc7d23406
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Always clear ETMCR[pwrdwn] while enabling trace. This is used as
a logic enable and is a pre-requisite while enabling trace. So
switch to an implementation that does this and removes the save
and restore for pwrdwn and pwrup.
Change-Id: I8a14efe8fd76368ed1e177a701013a504aa1876f
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
For better throughput and to avoid limitations, use 2K block size
tranfers when outputting data over usb using ETR. Moreover, USB 3.0
currently only supports 2K block size for the descriptors.
Change-Id: Idc68c4d503e3ccca7715d3cbec21daedfbc2df6f
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Add runtime control for enabling/disabling program counter save feature.
Enabling program counter save feature will enable pc to be saved on
reset but implies ETM being left powered on. So we provide user runtime
control to enable the feature when debugging or disable it while taking
power measurements.
Change-Id: Ib007da851ee7f3b0fac195da62aac7def68cc67a
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Explicitly clear and set ETMCR power down bit as part of the ETM
register programming sequence since if this bit is set, writes to
some registers and fields might be ignored.
Moreover, ETMCR prog and power down bits are not directly modifiable
via the sysfs based MODE selction code. Instead they can implicitly get
modified by other code. So always preserve their values while
enabling ETM trace since the ctrl is a shadow of ETMCR bits that
are only modifiable via the sysfs based MODE selection code.
Change-Id: I842a42acdafb112759a1787ec6fc41140812020d
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Enable and disable STM during probe to undo the effect of RPM
temporarily turning on STM to ETF path. This ensures that all
the coresight components from STM to the default compile time
sink (ETF) get disabled in probe thereby resulting in their
states to more closely correspond to their reset states.
This is necessary since coresight drivers are designed to assume
reset state (on a power on boot) for the devices they control.
Change-Id: I8707f6134de2488754fb01b5e2830588efa729cc
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Initialize buf for TMC ETR to the virtual address of the allocated
buffer memory. This will ensure a read on TMC ETR device node when ETF
is the current sink doesn't fail.
Change-Id: Id23dd9502ec728567c5b137354ca2d734f9309dc
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
coresight_abort allows for abruptly stopping the current sink from
accepting new data hence avoiding polluting trace with information
after the point of interest.
Depending upon the call site, coresight_abort could end up getting
called more than once. This change will help with ignoring
subsequent calls to coresight_abort so that abort callback is
called just once. This is in line with treating abort as a one time
abrupt stop.
Change-Id: I634001e832ee7fa1b23f67698bd2d5dd12f8d65d
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
This reverts commit 670627c323f1d6a72a35763d6b9dddca18f654df. We now
have cp14 based ETM support for Krait v3 so ETM tracing for Krait v3
can be turned on. This will enable ETM usage on Krait v3.
Change-Id: Ie7189c38d4aee43580ac145edceb8ffdbe8c9072
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Use cp14 accesses to ETM registers for Krait v3 to avoid
limitations with memory mapped accesses.
Change-Id: Ia956eb0f5b45c748ffb5dd13dd14dc9595b9c68a
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Use ETMPDCR instead of ETMCR for ETM power/clock enable/disable. ETMPDCR
doesn't have corresponding cp14 access and hence will help with subsequent
multicore ETM support changes for 8974. ETMPDCR is available for PFTv1.1
and ETMv3.5 compliant ETM implementations.
Change-Id: I4b190b963cda29b406971cf075db36213b140495
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
A DLKM to abort tracing on an user space data, prefetch or
undefined instruction abort.
Change-Id: Iaba14628601ea6d3649e05423f8570131eea39f7
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
Move etm_arch_supported out of etm_init_arch_data to simplify the
init flow.
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Change-Id: I8a95f59e35e74c5af8c447abdc9f0dcd1682bce1
Add support to allow debug image to be able to dump ETF content
and ETM, TMC regsiters in case of apps proc bite or system hang
causing secure watchdog reset.
This will enable host parsing scripts to extract ETF and
ETR-memory trace data contents from RAM dumps.
Change-Id: Ie6f03bef7b4ccda7ea8d7709ee0c4808424c5b92
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Instead of writing FFCR bits 12 and 6 at once, sequence them i.e.
write bit 12 first to set ETB to stop on flush and followed by
setting bit 6 to trigger manual flush.
This should avoid any possible race between flush completing
before bit 12 getting set.
Change-Id: I0567701d34cb33a35d6bd876636a296532b9e400
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Change STM traceid from 3 to 16 so that ETM and STM can be used
concurrently if required. ATIDs 0 to 15 are reserved for ETM - one
for each core.
Change-Id: Ic51cf3b8baa9c22be69c952a20281b238750de5d
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Since we moved to separate enable nodes for each ETM, using pm_qos
to prevent power collapse of the target cpu while we enable or
disable ETM is less efficient and also susceptible to a race with
cpu hotplug.
Move to using smp call to enable and disable trace to avoid above
deficiencies with the newly re-structured code.
Change-Id: I65c726dbd6275af8db0d40db5034299287a02e91
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Memory reservation is now required for carve outs. Add appropriate
memory reservation driver support for the TMC ETR carve out.
Change-Id: I31cda1317d31555b70a034eae4c6fdadacd36fdb
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
With maxcpus=1, only core0 will be running with other cores in
reset until they are explicitly hotplugged on. To avoid reading
ETM registers for cores that are in reset during probe, use only
ETM0 for populating configuration info. For other ETM probes,
copy the info from ETM0.
Change-Id: I9ae4539b004956a026e919323413f9e3c7d5ba4a
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Program STM to allow TRIGOUTHETE output (that feeds into the CTI input)
to be asserted when hardware events occur. Also program the STM sync
frequency to 1023 byte interval.
Change-Id: Ia4c9c73d61a50dfc5eb2df5f52921831b647df0e
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Ensure that buffer pointer points to the right location while
trying to read TMC in ETR circular buffer mode when we wrap
around.
TMC in ETR circular buffer mode tracks the physical address
in the RWP register (in contrast to pure offsets). Hence
subtract it from the base physical address to get the offset.
Change-Id: Ice1170dcd63928dd8304c421800848e036386b88
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Support for etr to usb trace output using QDSS BAM to USB BAM
transfers.
Change-Id: Ibb6f8d0cf1d9799668cb22ccaa13966139c8dea5
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Change CONFIG_MSM_QDSS to granular CORESIGHT configs covering
various CoreSight drivers. This better represents the CoreSight
device topology and allows more flexibility in choosing the
drivers required for a particular platform or chip.
Conflicts:
arch/arm/configs/msm8960-perf_defconfig
arch/arm/configs/msm8960_defconfig
arch/arm/configs/msm8974-perf_defconfig
arch/arm/configs/msm8974_defconfig
arch/arm/configs/msm9625_defconfig
arch/arm/mach-msm/Kconfig
drivers/coresight/Kconfig
drivers/coresight/Makefile
drivers/coresight/coresight-etm.c
drivers/coresight/coresight-priv.h
Change-Id: I5ae44442c24c88673f2045ad24dc89e4d86d23cb
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Memory mapped accesses to ETM registers on Krait pass3 cause
intermittent hangs that lock up all the Kraits and their T32
sessions.
This is currently under debug but until this is resolved
error out of ETM probe for Krait pass3.
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Signed-off-by: Joel King <joelking@codeaurora.org>
(cherry picked from commit 670627c323f1d6a72a35763d6b9dddca18f654df)
Change-Id: I563451964ae5b5afd72423c1a2cec391edc6142e
Signed-off-by: Sudhir Sharma <sudsha@codeaurora.org>
Bottom 8 bits [7:0] of ETMSYNCFR are reserved on Krait pass3. This
means only bits [11:8] are valid since bits [31:12] are specified
as reserved by PFTv1.1 specification.
Use an appropriate value for the synchronization frequency in light
of this change on Krait pass3.
Change-Id: I5f32ad6546fc8a72e0a222cc90e0f23c9779ee3c
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Have STM hardware event and port enable sysfs nodes to allow users to
selectively enable and disable either hardware events or stimulus
ports while STM as a whole is enabled.
Change-Id: I32c23f62a3782487e67eb5e6a9da5a5bf7e11df8
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Provide CoreSight abort debug api to stop the active trace sink
from any context. This is a best effort api that can be used to
abruptly stop and disable the current trace sink from anywhere
in the kernel to avoid tracing and hence polluting the trace data
after the point of interest has been executed.
Change-Id: I34c528d9febec4265088a7267dbcf0e7a1f87fcf
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
This driver manages CoreSight TMC (Trace Memory Controller) which
can be pre-configured as an ETF (Embedded Trace FIFO) or ETR
(Embedded Trace Router). ETF when configured in circular buffer mode
acts as an ETB (Embedded Trace Buffer).
Change-Id: I1ca40e1fbd3049dc7addb834c064ab3a6c4c22e0
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Support for reading hardware data for CoreSight devices from device
tree.
Change-Id: I4d149991c89b458384465d163386084f500a4028
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Using devm_* apis helps in simplifying driver init and exit paths,
hence switch to using them in the driver probe calls.
Change-Id: I41aba1129f6638fcee859e57f957fa3f14c1c439
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
This driver manages the CoreSight Replicator that has been made
programmable to allow software to turn of the replicator branch
to sink that is not being used. This avoids trace traffic to the
unused/non-current sink from causing backpressure that results in
overflows at the source.
Change-Id: Idf82149d5dc3702b6da59147e4d9d5e532032161
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Switch all CoreSight drivers to start using the new CoreSight core
layer code. Remove obsolete qdss code.
Change-Id: I2d4496aea0ffd918e0bfbf4b4e58ad82ea634a59
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Some targets require tpiu is disabled before other sinks like ETB
get enabled to get proper ETM trace.
Change-Id: Idcacf7b6515fd17c3a49c74a338258f02631f7cc
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
This allows users to switch between available trace sinks thus
providing user to choose the best switch for the debug use case.
Change-Id: I0c90396010cfcd9f3ab9d3c6d4c1cc7230632c42
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Complete the rename by changing cs to coresight for variables,
functions and constants.
Change-Id: I506d5872e5c09f201c4f3674d7722d36eca26921
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Since cs is not a well known acronym for CoreSight, rename
directory and files from cs to coresight.
Change-Id: I5f9b12794b80b1c01c9ce0621d53ee6be408a361
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
