Resource aqquistion on a per transfer level incures
a noticable latency penalty. This change removes
this latency by doing resource aqquisition as part
of runtime-pm on non-shared cores.
Change-Id: I112c10f52342ca7143b2286c72bba49ba7c8e49f
Signed-off-by: Dan Sneddon <dsneddon@codeaurora.org>
Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
Add support for the same spi controller to be programmed
by the CPU and other execution environments rather than the
controller hw being owned by only one ee.
Change-Id: Id6560b9cb09ddf59045fdf48c713d14c5c013145
Signed-off-by: Dan Sneddon <dsneddon@codeaurora.org>
Signed-off-by: Pradosh Das <prados@codeaurora.org>
Prevent spi transfers from being grouped together.
Grouping multiple transfers together causes invalid
write then read transactions. This patch prevents
the transactions from being grouped and ensures the
chipselect toggles appropriately.
CRs-Fixed: 661007
Change-Id: I1962cc95fde196295f37c64ecd54e490a7285bc4
Signed-off-by: Dan Sneddon <dsneddon@codeaurora.org>
Due to missing initialization of wait queue
issues reported on customer builds. This patch
adds the missing wait queue initialization code.
Change-Id: I2150d94bfec74b26842aac4fbd0e2e44af3b9943
Signed-off-by: Sana Venkat Raju <c_vsana@codeaurora.org>
Spi doesn't handle multiple xfer per message scenario
(eg:Rd->Wr or Wr->Rd) correctly and spi request
stuck indefinetly in while loop when total byte count
is not 0.
increment both(rx,tx) references so next bam
transaction will be queued correctly. Flush the
bam pipes after each transactions.
CRs-Fixed: 637693
Change-Id: I455df38be2f9687b1eb2a704466f6974dfb83a22
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
Add support to use new message queue feature provided
by SPI core framework. It is having benefits of saving
code space and getting the benefits of improvements
implemented in the core. User can set the priority
of message queue at compile time.
CRs-Fixed: 458268
Change-Id: I3f3a70b20ed6f2c8ceb9c27d616c5ba19acb422c
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
Signed-off-by: Sana Venkat Raju <c_vsana@codeaurora.org>
Message queue is scheduled to process
SPI messages during system suspend
state which leads to crash.
This patch make sure all the messages
in queue are processed before system
suspends.
CRs-Fixed: 593658
Change-Id: I722f24fcee4a1d2bbfee4341c8bc6c36ff9e1ec8
Signed-off-by: Sana Venkat Raju <c_vsana@codeaurora.org>
Currently SPI driver is queuing a single BAM descriptor
at a time. The BAM engine supports queuing of multiple
transfer descriptors.
Add support to spi driver to queue multiple descriptors.
CRs-Fixed: 546346
Change-Id: Iaee9b3b362832262b75e46e19ad18552d037620b
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
Signed-off-by: Sana Venkat Raju <c_vsana@codeaurora.org>
QUP_IRQ complete is triggered before dmov_rx callback.
Which will initiate SPI to start next transfer, due to
this earlier DMOV_CMD is blocked and results in kernel panic.
Current Implementation make sure that transfer complete waits
For DMOV callback only in case of aligned lengths ,This patch
ensures transfer trigger only after DMOV RX call back for
unaligned length also.
CRs-Fixed: 583126
Change-Id: I306a705d0eaf0eac33b2dbf335992254351cce20
Signed-off-by: Sana Venkat Raju <c_vsana@codeaurora.org>
The HW is not mandating the use of input first in bam mode,
therefore, that statement is removed.
CRs-Fixed: 519665
Change-Id: I7c5bbe8a71ea5b8a0e25efdea585251c7c4d4d14
Signed-off-by: Gilad Avidov <gavidov@codeaurora.org>
During probe Chip select gpio's valid field is set to non-zero.
This is causing gpio free to get called for not-used gpios
during runtime suspend.
CRs-Fixed: 525743
Change-Id: Ib0de417d640f30908ad11650b584833dac286646
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
When reading values from the device tree, the error
check on BAM producer pipe must be negated.
Change-Id: Ia766cabdde47390c5a3c79b1c98a704e695fc571
Signed-off-by: Gilad Avidov <gavidov@codeaurora.org>
Sometimes system suspend is initiated before runtime
PM's auto-suspend delay expires and causing devices to
not suspended runtime. As part of system suspend if
device is not suspended runtime then clocks and gpios
are manages by system suspend.
If spi client does initiate transaction request immediately
after system resume then spi doesn't resume run-time
immediately as spi controller's device state is not in
'suspended state'.
Keep device's runtime PM status to suspended during
system suspend.
CRs-Fixed: 512718
Change-Id: I5c0cb39c0b91782d8686c1b3da81125169ccf9be
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
Redirection on a NULL pointer leads to a system crash.
Here we verify pointers which potentially may be NULL
before a redirection.
Change-Id: I72b856e52f63b13e517c28d8dbb04e1f333f8065
Signed-off-by: Gilad Avidov <gavidov@codeaurora.org>
BAM pipes must be flushed when a transfer timeout
leaving dangling descriptors.
Change-Id: I29fbd2a98964bff5496630a165b3cd0a3f1f2d08
Signed-off-by: Gilad Avidov <gavidov@codeaurora.org>
Currently GPIOs are identified (MISO/MOSI/CLK or CS0..3)
by their index in the device-tree entry's array.
Further, chipselect GPIOs must be declared in order.
This allows to set a value for GPIO number three only
if the values for GPIOs one and two are also set.
This patch allows the driver to identify GPIOs by a
unique name, thus allows to specify any arbitrary
chipselect GPIO and reduces chances of simple
user configuration error.
Change-Id: I7cf1fb4329155bd5fc635257fc58d1dfa7312462
Signed-off-by: Gilad Avidov <gavidov@codeaurora.org>
Currently the spi driver votes for its core clock. However, it is
possible that the core-clock's source will be off. When the source
is off, the spi core is not clocked. This patch adds voting for
the entire clock path, thus guarantee clocking to the spi core.
Voting for the path cost a few msecs. A client may choose when
to pay this overhead. By default the votes takes place in the
runtime-pm callbacks which tie to transaction requests. A client
may choose to invoke these callbacks itself whenever it likes
by directly calling the driver's runtime-pm. A third option is
to set the active_only flag in platform data which results in the
callbacks being called when the application processor power state
changes.
CRs-Fixed: 478465
Change-Id: Ib866399c0e84a875a19a0d1506d77bbe77d5fe61
Signed-off-by: Gilad Avidov <gavidov@codeaurora.org>
The SPI mini-core has a specialized signal sampling mode which
improves signal to noise ratio for bus rates that are greater
then or equal to 26MHz.
This patch sets the mini-core in high-speed mode whan
the bus rate is greater or equal to this limit.
CRs-Fixed: 460451
Change-Id: I9a5094c92f3be8b683cd28a7737501d26b45b082
Signed-off-by: Gilad Avidov <gavidov@codeaurora.org>
Enable and disable the clocks and gpios to the SPI controller
using runtime PM. This serves the dual purpose of reducing power
Consumption a little and letting the core know when the device is idle.
If runtime_pm is not supported, then make sure the device becomes
active in first transaction after system-suspend, instead of
system-resume.
CRs-Fixed: 460988
Change-Id: I2360b6f48491cd0e8e5f1ce54805079daf92e36b
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
Due to a bug in the if() condition msm_spi_use_dma
function is always returning '0' when cs_change
is true. Due to this issue the DMA mode is not being used
when it has to be.
CRs-Fixed: 475841
Change-Id: I7da2ee091635f0cfd89058787c35b62adf1984b5
Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
Updated BAM security setting prohibit direct control of
BAM HW from the execution environment which runs the Kernel.
This patch utilises the BAM's driver support for satellite
-mode which, transparently, controls the BAM from a permitted
execution environment.
Change-Id: I56aab2ba934fa8854fa0202d6766d079f9d0fcb9
Signed-off-by: Gilad Avidov <gavidov@codeaurora.org>
SPI driver doesn't support different block size in
DM mode because based on assumption that GSBI tx&rx
FIFOs are of same size. Some GSBI configuration
can have different tx/rx fifo size. Tx/Rx fifo size
is defined based on input/output block size.
Adds support for different rx/tx fifo size in
case of DMA transaction.
CRs-Fixed: 452986
Change-Id: Ie86f487ea97037ed14e9838a3bd52dfe95f56974
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
Update device tree entries to comply with latest practice.
Change proprietary entry name from "infinite_mode" to
"qcom,infinite-mode" and specify bus-number by alias instead
of "cell-index". The following changes are updated to spi's
device-tree binding document.
CRs-Fixed: 451911
Change-Id: Id54d494c23578315b04e7682fe3a815c7db1b421
Signed-off-by: Gilad Avidov <gavidov@codeaurora.org>
Specifying max clock frequency for SPI, via platform data, requires
a frequency that is available to SPI. The frequencies that are
available to SPI and the devices max-frequency are specified in
different places and in different files. As a result theses values
can easily go out of sync.
SPI devices typically can operate at some maximum frequency, with
some tolerance for the actual-frequency being lower. SPI users
typically know their target-device's max-speed, but they have
to dig in platform data files to find the best matching frequency
that is available.
This patch lets users specify the device's max-frequency, while the
actual frequency is automatically selected by the driver. The selected
frequency is the same as the requested one, or the nearest lower one.
Change-Id: I293ec1b66ad56e4a2b4643482917f79dabd7a758
Signed-off-by: Gilad Avidov <gavidov@codeaurora.org>
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
Call the dma_teardown callback on the error path only if
one has been registered.
Change-Id: I9c5c9d59ea504be9417be089d6d3055a230a482f
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Client has ability to request delay per transfer through SPI
framework. SPI controller driver needs to put this delay after every
transfer. However, this also means that multiple transfers per message
cannot be combined to be able to insert this delay per transfer.
CS will be de-asserted after completion of each transfer
on older version of QUP/SPI core.
CRs-fixed: 416186
Change-Id: Id9266ce7043e020fa7e1233c66baba30ba3d496c
Signed-off-by: Gilad Avidov <gavidov@codeaurora.org>
Signed-off-by: Sagar Dharia <sdharia@codeaurora.org>
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
The new SPI QUP-core version-2, adds support to a new DMA
engine, adds a new register, and introduces some changes to
existing registers. The new BAM DMA engine supersedes the
older Data-Mover DMA engine. The new register, the hardware-
version register, is used by the patch to query the hardware
about its precise version. Using the precise version the driver
may verify HW support for the BAM mode.
This patch keeps backward compatibility with older
Qualcomm SPI-controllers exisiting in and QUP-core-ver-1 and
pre-QUP cores. The new QUP-core-ver-2 features three transfer
modes each optimized for a different transfer size: FIFO-mode for
small transfers, Block-mode for mid-size transfers, and BAM mode
for large size transfers. The current SPI driver supports only FIFO
mode. This mode is utilized for transfers of all sized. This patch
enables BAM-mode for mid to large size transfers. Using of the
BAM engine for large transfers, reliefs the CPU of slow IO
operations.
The patch relies on new platform-specific-data entries to read
values for BAM configuration.
Change-Id: I8baa89e6e33197c6265ab7f38965e7c3e10e80f8
Signed-off-by: Gilad Avidov <gavidov@codeaurora.org>
Configure the spi clk, mosi, miso, cs gpio's on per
transaction basis and unconfigure otherwise.
It will remove the conflicts if same gpio's are
being used by different modules if no SPI device
is present.
CRs-Fixed: 387043
Change-Id: Ib5c3bfbd13681f4aee0c4a815b19f423c586e160
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
Support to transfer 64K bytes in a single SPI
transfer in DMA mode on targets which support
16 bits in QUP_MX_OUTPUT_CNT register. Earlier
if the application sends more than 4K data it is
split up in to 4K chunks, irrespective of the size
of the QUP_MX_OUTPUT_CNT register.
CRs-Fixed: 383120
Change-Id: Ibbe73df2bb4fb2804ff6ebfc62adac9d0d53e9cd
Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
When using device tree, the bus number needs to be set based on the
cell-index property rather than the 'id' from the platform device.
This makes sure that the SPI bus number is set correctly.
Change-Id: I4489c28363a7fd79f3bc3db76207a1bc8ef507cb
Signed-off-by: Kenneth Heitke <kheitke@codeaurora.org>
If infinite mode is not supported, chip select goes
high after every 4k bytes. Make sure the same behavior
does not happen on targets that support infinite mode.
CRs-Fixed: 361961
Change-Id: I5cfea96202718214a8edd060e06fbb7fb2fa90a2
Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
AU_LINUX_ANDROID_ICS.04.00.04.00.126 from msm-3.0.
First parent is from google/android-3.4.
* commit 'AU_LINUX_ANDROID_ICS.04.00.04.00.126': (8712 commits)
PRNG: Device tree entry for qrng device.
vidc:1080p: Set video core timeout value for Thumbnail mode
msm: sps: improve the debugging support in SPS driver
board-8064 msm: Overlap secure and non secure video firmware heaps.
msm: clock: Add handoff ops for 7x30 and copper XO clocks
msm_fb: display: Wait for external vsync before DTV IOMMU unmap
msm: Fix ciruclar dependency in debug UART settings
msm: gdsc: Add GDSC regulator driver for msm-copper
defconfig: Enable Mobicore Driver.
mobicore: Add mobicore driver.
mobicore: rename variable to lower case.
mobicore: rename folder.
mobicore: add makefiles
mobicore: initial import of kernel driver
ASoC: msm: Add SLIMBUS_2_RX CPU DAI
board-8064-gpio: Update FUNC for EPM SPI CS
msm_fb: display: Remove chicken bit config during video playback
mmc: msm_sdcc: enable the sanitize capability
msm-fb: display: lm2 writeback support on mpq platfroms
msm_fb: display: Disable LVDS phy & pll during panel off
...
Signed-off-by: Steve Muckle <smuckle@codeaurora.org>
There may be some latency in the DMA IRQ firing in hardware.
Hence, in the case of write transfers, the QUP interrupt handler
waits for the DMA callback before issuing completion.
Change-Id: I4962c5c04c3a45dbf6e98165d2815adda657a9fb
Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
Use of/gpio routines to retrieve the gpios specified in
the device tree.
Change-Id: I77d09a36ba2513bbb476d2dd0b768828b22ab436
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
The graceful argument allows clients to specify whether they want
to flush now, or wait until the end of the current scatter gather or
box mode descriptor. This also helps us unify msm_dmov_flush and
msm_dmov_stop_cmd.
Change-Id: Ifdfe5da804e79343782cc2999ad3624d2afbec4d
Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org>
This patch ensures that the last bit of a transfer gets correctly
flushed out of the register.
Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
This condition is used to determine 8 bits or 16 and 32 bits transfer.
Obviously it is reversed.
Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
