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android_kernel_samsung_msm8976/drivers/base/regmap/regmap-irq.c

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regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
/*
* regmap based irq_chip
*
* Copyright 2011 Wolfson Microelectronics plc
*
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/export.h>
device.h: cleanup users outside of linux/include (C files) For files that are actively using linux/device.h, make sure that they call it out. This will allow us to clean up some of the implicit uses of linux/device.h within include/* without introducing build regressions. Yes, this was created by "cheating" -- i.e. the headers were cleaned up, and then the fallout was found and fixed, and then the two commits were reordered. This ensures we don't introduce build regressions into the git history. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2012-01-22 16:23:42 +00:00
#include <linux/device.h>
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
#include <linux/regmap.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
regmap: Convert regmap_irq to use irq_domain This gets us up to date with the recommended current kernel infrastructure and should transparently give us device tree interrupt bindings for any devices using the framework. If an explicit IRQ mapping is passed in then a legacy interrupt range is created, otherwise a simple linear mapping is used. Previously a mapping was mandatory so existing drivers should not be affected. A function regmap_irq_get_virq() is provided to allow drivers to map individual IRQs which should be used in preference to the existing regmap_irq_chip_get_base() which is only valid if a legacy IRQ range is provided. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-05-13 09:59:56 +00:00
#include <linux/irqdomain.h>
regmap: irq: Enable devices for runtime PM while handling interrupts Some devices need to have a runtime PM reference while handling interrupts to ensure that the register I/O is available. Support this with a flag in the chip. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-07-24 14:41:19 +00:00
#include <linux/pm_runtime.h>
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
#include <linux/slab.h>
#include "internal.h"
struct regmap_irq_chip_data {
struct mutex lock;
regmap: store irq_chip inside regmap_irq_chip_data This will allow later patches to adjust portions of the irq_chip individually for each regmap_irq_chip that is created. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-08-01 17:40:47 +00:00
struct irq_chip irq_chip;
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
struct regmap *map;
regmap: Constify regmap_irq_chip We should never be modifying it and it lets drivers declare it const. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-05-31 20:01:46 +00:00
const struct regmap_irq_chip *chip;
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
int irq_base;
regmap: Convert regmap_irq to use irq_domain This gets us up to date with the recommended current kernel infrastructure and should transparently give us device tree interrupt bindings for any devices using the framework. If an explicit IRQ mapping is passed in then a legacy interrupt range is created, otherwise a simple linear mapping is used. Previously a mapping was mandatory so existing drivers should not be affected. A function regmap_irq_get_virq() is provided to allow drivers to map individual IRQs which should be used in preference to the existing regmap_irq_chip_get_base() which is only valid if a legacy IRQ range is provided. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-05-13 09:59:56 +00:00
struct irq_domain *domain;
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
regmap: Implement support for wake IRQs Allow chips to provide a bank of registers for controlling the wake state in a similar fashion to the masks and propagate the wake count to the parent interrupt controller. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-06-05 13:34:03 +00:00
int irq;
int wake_count;
regmap: irq: Use a bulk read for interrupt status where possible If the interrupt status registers are a single block of registers and the chip supports bulk reads then do a single bulk read rather than pay the extra I/O cost. This restores the original behaviour which was lost when support for register striding was added. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2013-01-03 14:27:15 +00:00
void *status_reg_buf;
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
unsigned int *status_buf;
unsigned int *mask_buf;
unsigned int *mask_buf_def;
regmap: Implement support for wake IRQs Allow chips to provide a bank of registers for controlling the wake state in a similar fashion to the masks and propagate the wake count to the parent interrupt controller. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-06-05 13:34:03 +00:00
unsigned int *wake_buf;
regmap: add support for non contiguous status to regmap-irq In some chips the IRQ status registers are not contiguous in the register map but spaced at even spaces. This is an easy case to handle with minor changes. It is assume for this purpose that the stride for status is equal to the stride for mask/ack registers as well. Signed-off-by: Graeme Gregory <gg@slimlogic.co.uk> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-05-14 13:40:43 +00:00
unsigned int irq_reg_stride;
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
};
static inline const
struct regmap_irq *irq_to_regmap_irq(struct regmap_irq_chip_data *data,
int irq)
{
regmap: Convert regmap_irq to use irq_domain This gets us up to date with the recommended current kernel infrastructure and should transparently give us device tree interrupt bindings for any devices using the framework. If an explicit IRQ mapping is passed in then a legacy interrupt range is created, otherwise a simple linear mapping is used. Previously a mapping was mandatory so existing drivers should not be affected. A function regmap_irq_get_virq() is provided to allow drivers to map individual IRQs which should be used in preference to the existing regmap_irq_chip_get_base() which is only valid if a legacy IRQ range is provided. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-05-13 09:59:56 +00:00
return &data->chip->irqs[irq];
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
}
static void regmap_irq_lock(struct irq_data *data)
{
struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
mutex_lock(&d->lock);
}
static void regmap_irq_sync_unlock(struct irq_data *data)
{
struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
regmap: fix compile errors in regmap-irq.c due to stride changes Commit f01ee60fffa4 ("regmap: implement register striding") caused the compile errors below. Fix them. drivers/base/regmap/regmap-irq.c: In function 'regmap_irq_sync_unlock': drivers/base/regmap/regmap-irq.c:62:12: error: 'map' undeclared (first use in this function) drivers/base/regmap/regmap-irq.c:62:12: note: each undeclared identifier is reported only once for each function it appears in drivers/base/regmap/regmap-irq.c: In function 'regmap_irq_enable': drivers/base/regmap/regmap-irq.c:77:37: error: 'map' undeclared (first use in this function) drivers/base/regmap/regmap-irq.c: In function 'regmap_irq_disable': drivers/base/regmap/regmap-irq.c:85:37: error: 'map' undeclared (first use in this function) Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-04-11 05:37:22 +00:00
struct regmap *map = d->map;
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
int i, ret;
regmap: fix some error messages to take account of irq_reg_stride A number of places in the code were printing error messages that included the address of a register, but were not calculating the register address in the same way as the access to the register. Use a temporary to solve this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-07-27 19:01:54 +00:00
u32 reg;
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
regmap: irq: Enable devices for runtime PM while handling interrupts Some devices need to have a runtime PM reference while handling interrupts to ensure that the register I/O is available. Support this with a flag in the chip. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-07-24 14:41:19 +00:00
if (d->chip->runtime_pm) {
ret = pm_runtime_get_sync(map->dev);
if (ret < 0)
dev_err(map->dev, "IRQ sync failed to resume: %d\n",
ret);
}
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
/*
* If there's been a change in the mask write it back to the
* hardware. We rely on the use of the regmap core cache to
* suppress pointless writes.
*/
for (i = 0; i < d->chip->num_regs; i++) {
regmap: fix some error messages to take account of irq_reg_stride A number of places in the code were printing error messages that included the address of a register, but were not calculating the register address in the same way as the access to the register. Use a temporary to solve this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-07-27 19:01:54 +00:00
reg = d->chip->mask_base +
(i * map->reg_stride * d->irq_reg_stride);
regmap: irq: Add mask invert flag for enable register Currently, regmap will write 1 to mask_base to mask an interrupt and write 0 to unmask it. But some chips do not have an interrupt mask register, and only have interrupt enable register. Then we should write 0 to disable interrupt and 1 to enable. So add an mask_invert flag to handle this. If it is not set, behavior is same as previous. If set it to 1, the mask value will be inverted before written to mask_base Signed-off-by: Xiaofan Tian <tianxf@marvell.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-08-30 09:03:35 +00:00
if (d->chip->mask_invert)
ret = regmap_update_bits(d->map, reg,
d->mask_buf_def[i], ~d->mask_buf[i]);
else
ret = regmap_update_bits(d->map, reg,
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
d->mask_buf_def[i], d->mask_buf[i]);
if (ret != 0)
dev_err(d->map->dev, "Failed to sync masks in %x\n",
regmap: fix some error messages to take account of irq_reg_stride A number of places in the code were printing error messages that included the address of a register, but were not calculating the register address in the same way as the access to the register. Use a temporary to solve this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-07-27 19:01:54 +00:00
reg);
regmap: irq: Fix sync of wake statuses to hardware This wasn't implemented but happened to work on test systems due to lack of wake mask inversion support. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2013-01-04 16:32:54 +00:00
reg = d->chip->wake_base +
(i * map->reg_stride * d->irq_reg_stride);
if (d->wake_buf) {
regmap: irq: Support wake IRQ mask inversion Support devices which have an enable rather than mask register for wake sources. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2013-01-04 16:35:07 +00:00
if (d->chip->wake_invert)
ret = regmap_update_bits(d->map, reg,
d->mask_buf_def[i],
~d->wake_buf[i]);
else
ret = regmap_update_bits(d->map, reg,
d->mask_buf_def[i],
d->wake_buf[i]);
regmap: irq: Fix sync of wake statuses to hardware This wasn't implemented but happened to work on test systems due to lack of wake mask inversion support. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2013-01-04 16:32:54 +00:00
if (ret != 0)
dev_err(d->map->dev,
"Failed to sync wakes in %x: %d\n",
reg, ret);
}
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
}
regmap: irq: Enable devices for runtime PM while handling interrupts Some devices need to have a runtime PM reference while handling interrupts to ensure that the register I/O is available. Support this with a flag in the chip. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-07-24 14:41:19 +00:00
if (d->chip->runtime_pm)
pm_runtime_put(map->dev);
regmap: Implement support for wake IRQs Allow chips to provide a bank of registers for controlling the wake state in a similar fashion to the masks and propagate the wake count to the parent interrupt controller. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-06-05 13:34:03 +00:00
/* If we've changed our wakeup count propagate it to the parent */
if (d->wake_count < 0)
for (i = d->wake_count; i < 0; i++)
irq_set_irq_wake(d->irq, 0);
else if (d->wake_count > 0)
for (i = 0; i < d->wake_count; i++)
irq_set_irq_wake(d->irq, 1);
d->wake_count = 0;
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
mutex_unlock(&d->lock);
}
static void regmap_irq_enable(struct irq_data *data)
{
struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
regmap: fix compile errors in regmap-irq.c due to stride changes Commit f01ee60fffa4 ("regmap: implement register striding") caused the compile errors below. Fix them. drivers/base/regmap/regmap-irq.c: In function 'regmap_irq_sync_unlock': drivers/base/regmap/regmap-irq.c:62:12: error: 'map' undeclared (first use in this function) drivers/base/regmap/regmap-irq.c:62:12: note: each undeclared identifier is reported only once for each function it appears in drivers/base/regmap/regmap-irq.c: In function 'regmap_irq_enable': drivers/base/regmap/regmap-irq.c:77:37: error: 'map' undeclared (first use in this function) drivers/base/regmap/regmap-irq.c: In function 'regmap_irq_disable': drivers/base/regmap/regmap-irq.c:85:37: error: 'map' undeclared (first use in this function) Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-04-11 05:37:22 +00:00
struct regmap *map = d->map;
regmap: Convert regmap_irq to use irq_domain This gets us up to date with the recommended current kernel infrastructure and should transparently give us device tree interrupt bindings for any devices using the framework. If an explicit IRQ mapping is passed in then a legacy interrupt range is created, otherwise a simple linear mapping is used. Previously a mapping was mandatory so existing drivers should not be affected. A function regmap_irq_get_virq() is provided to allow drivers to map individual IRQs which should be used in preference to the existing regmap_irq_chip_get_base() which is only valid if a legacy IRQ range is provided. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-05-13 09:59:56 +00:00
const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
regmap: implement register striding regmap_config.reg_stride is introduced. All extant register addresses are a multiple of this value. Users of serial-oriented regmap busses will typically set this to 1. Users of the MMIO regmap bus will typically set this based on the value size of their registers, in bytes, so 4 for a 32-bit register. Throughout the regmap code, actual register addresses are used. Wherever the register address is used to index some array of values, the address is divided by the stride to determine the index, or vice-versa. Error- checking is added to all entry-points for register address data to ensure that register addresses actually satisfy the specified stride. The MMIO bus ensures that the specified stride is large enough for the register size. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-04-09 19:40:24 +00:00
d->mask_buf[irq_data->reg_offset / map->reg_stride] &= ~irq_data->mask;
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
}
static void regmap_irq_disable(struct irq_data *data)
{
struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
regmap: fix compile errors in regmap-irq.c due to stride changes Commit f01ee60fffa4 ("regmap: implement register striding") caused the compile errors below. Fix them. drivers/base/regmap/regmap-irq.c: In function 'regmap_irq_sync_unlock': drivers/base/regmap/regmap-irq.c:62:12: error: 'map' undeclared (first use in this function) drivers/base/regmap/regmap-irq.c:62:12: note: each undeclared identifier is reported only once for each function it appears in drivers/base/regmap/regmap-irq.c: In function 'regmap_irq_enable': drivers/base/regmap/regmap-irq.c:77:37: error: 'map' undeclared (first use in this function) drivers/base/regmap/regmap-irq.c: In function 'regmap_irq_disable': drivers/base/regmap/regmap-irq.c:85:37: error: 'map' undeclared (first use in this function) Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-04-11 05:37:22 +00:00
struct regmap *map = d->map;
regmap: Convert regmap_irq to use irq_domain This gets us up to date with the recommended current kernel infrastructure and should transparently give us device tree interrupt bindings for any devices using the framework. If an explicit IRQ mapping is passed in then a legacy interrupt range is created, otherwise a simple linear mapping is used. Previously a mapping was mandatory so existing drivers should not be affected. A function regmap_irq_get_virq() is provided to allow drivers to map individual IRQs which should be used in preference to the existing regmap_irq_chip_get_base() which is only valid if a legacy IRQ range is provided. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-05-13 09:59:56 +00:00
const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
regmap: implement register striding regmap_config.reg_stride is introduced. All extant register addresses are a multiple of this value. Users of serial-oriented regmap busses will typically set this to 1. Users of the MMIO regmap bus will typically set this based on the value size of their registers, in bytes, so 4 for a 32-bit register. Throughout the regmap code, actual register addresses are used. Wherever the register address is used to index some array of values, the address is divided by the stride to determine the index, or vice-versa. Error- checking is added to all entry-points for register address data to ensure that register addresses actually satisfy the specified stride. The MMIO bus ensures that the specified stride is large enough for the register size. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-04-09 19:40:24 +00:00
d->mask_buf[irq_data->reg_offset / map->reg_stride] |= irq_data->mask;
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
}
regmap: Implement support for wake IRQs Allow chips to provide a bank of registers for controlling the wake state in a similar fashion to the masks and propagate the wake count to the parent interrupt controller. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-06-05 13:34:03 +00:00
static int regmap_irq_set_wake(struct irq_data *data, unsigned int on)
{
struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
struct regmap *map = d->map;
const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
if (on) {
regmap: irq: enable wake support by default regmap-irq framework is used vastly by mfd drivers and some of devices like TPS65910, TPS80036 do not support the wake base register to enable wake. Currently wake in regmap-irq only supported if client driver passes the wake base register. As the regmap-irq is mostly used by mfd devices and it is require to have wake support from these devices in most of use cases, enabling wake support by default in regmap-irq. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-12-19 14:12:28 +00:00
if (d->wake_buf)
d->wake_buf[irq_data->reg_offset / map->reg_stride]
&= ~irq_data->mask;
regmap: Implement support for wake IRQs Allow chips to provide a bank of registers for controlling the wake state in a similar fashion to the masks and propagate the wake count to the parent interrupt controller. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-06-05 13:34:03 +00:00
d->wake_count++;
} else {
regmap: irq: enable wake support by default regmap-irq framework is used vastly by mfd drivers and some of devices like TPS65910, TPS80036 do not support the wake base register to enable wake. Currently wake in regmap-irq only supported if client driver passes the wake base register. As the regmap-irq is mostly used by mfd devices and it is require to have wake support from these devices in most of use cases, enabling wake support by default in regmap-irq. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-12-19 14:12:28 +00:00
if (d->wake_buf)
d->wake_buf[irq_data->reg_offset / map->reg_stride]
|= irq_data->mask;
regmap: Implement support for wake IRQs Allow chips to provide a bank of registers for controlling the wake state in a similar fashion to the masks and propagate the wake count to the parent interrupt controller. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-06-05 13:34:03 +00:00
d->wake_count--;
}
return 0;
}
regmap: store irq_chip inside regmap_irq_chip_data This will allow later patches to adjust portions of the irq_chip individually for each regmap_irq_chip that is created. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-08-01 17:40:47 +00:00
static const struct irq_chip regmap_irq_chip = {
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
.irq_bus_lock = regmap_irq_lock,
.irq_bus_sync_unlock = regmap_irq_sync_unlock,
.irq_disable = regmap_irq_disable,
.irq_enable = regmap_irq_enable,
regmap: Implement support for wake IRQs Allow chips to provide a bank of registers for controlling the wake state in a similar fashion to the masks and propagate the wake count to the parent interrupt controller. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-06-05 13:34:03 +00:00
.irq_set_wake = regmap_irq_set_wake,
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
};
static irqreturn_t regmap_irq_thread(int irq, void *d)
{
struct regmap_irq_chip_data *data = d;
regmap: Constify regmap_irq_chip We should never be modifying it and it lets drivers declare it const. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-05-31 20:01:46 +00:00
const struct regmap_irq_chip *chip = data->chip;
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
struct regmap *map = data->map;
int ret, i;
regmap: Report if we actually handled an interrupt in regmap-irq While the IRQ core doesn't currently support shared threaded interrupts that's no reason for drivers not to do their bit and report IRQ_NONE when they don't get an interrupt. This allows the core spurious/wedget interrupt detection support to do its thing. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-11-28 18:50:39 +00:00
bool handled = false;
regmap: fix some error messages to take account of irq_reg_stride A number of places in the code were printing error messages that included the address of a register, but were not calculating the register address in the same way as the access to the register. Use a temporary to solve this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-07-27 19:01:54 +00:00
u32 reg;
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
regmap: irq: Enable devices for runtime PM while handling interrupts Some devices need to have a runtime PM reference while handling interrupts to ensure that the register I/O is available. Support this with a flag in the chip. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-07-24 14:41:19 +00:00
if (chip->runtime_pm) {
ret = pm_runtime_get_sync(map->dev);
if (ret < 0) {
dev_err(map->dev, "IRQ thread failed to resume: %d\n",
ret);
regmap: irq: call pm_runtime_put in pm_runtime_get_sync failed case Even in failed case of pm_runtime_get_sync, the usage_count is incremented. In order to keep the usage_count with correct value and runtime power management to behave correctly, call pm_runtime_put(_sync) in such case. Signed-off-by Liu Chuansheng <chuansheng.liu@intel.com> Signed-off-by: Li Fei <fei.li@intel.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2013-02-28 07:37:11 +00:00
pm_runtime_put(map->dev);
regmap: irq: Enable devices for runtime PM while handling interrupts Some devices need to have a runtime PM reference while handling interrupts to ensure that the register I/O is available. Support this with a flag in the chip. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-07-24 14:41:19 +00:00
return IRQ_NONE;
}
}
regmap: irq: Use a bulk read for interrupt status where possible If the interrupt status registers are a single block of registers and the chip supports bulk reads then do a single bulk read rather than pay the extra I/O cost. This restores the original behaviour which was lost when support for register striding was added. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2013-01-03 14:27:15 +00:00
/*
* Read in the statuses, using a single bulk read if possible
* in order to reduce the I/O overheads.
*/
if (!map->use_single_rw && map->reg_stride == 1 &&
data->irq_reg_stride == 1) {
u8 *buf8 = data->status_reg_buf;
u16 *buf16 = data->status_reg_buf;
u32 *buf32 = data->status_reg_buf;
regmap: add support for non contiguous status to regmap-irq In some chips the IRQ status registers are not contiguous in the register map but spaced at even spaces. This is an easy case to handle with minor changes. It is assume for this purpose that the stride for status is equal to the stride for mask/ack registers as well. Signed-off-by: Graeme Gregory <gg@slimlogic.co.uk> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-05-14 13:40:43 +00:00
regmap: irq: Use a bulk read for interrupt status where possible If the interrupt status registers are a single block of registers and the chip supports bulk reads then do a single bulk read rather than pay the extra I/O cost. This restores the original behaviour which was lost when support for register striding was added. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2013-01-03 14:27:15 +00:00
BUG_ON(!data->status_reg_buf);
ret = regmap_bulk_read(map, chip->status_base,
data->status_reg_buf,
chip->num_regs);
regmap: add support for non contiguous status to regmap-irq In some chips the IRQ status registers are not contiguous in the register map but spaced at even spaces. This is an easy case to handle with minor changes. It is assume for this purpose that the stride for status is equal to the stride for mask/ack registers as well. Signed-off-by: Graeme Gregory <gg@slimlogic.co.uk> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-05-14 13:40:43 +00:00
if (ret != 0) {
dev_err(map->dev, "Failed to read IRQ status: %d\n",
regmap: irq: Use a bulk read for interrupt status where possible If the interrupt status registers are a single block of registers and the chip supports bulk reads then do a single bulk read rather than pay the extra I/O cost. This restores the original behaviour which was lost when support for register striding was added. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2013-01-03 14:27:15 +00:00
ret);
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
return IRQ_NONE;
}
regmap: irq: Use a bulk read for interrupt status where possible If the interrupt status registers are a single block of registers and the chip supports bulk reads then do a single bulk read rather than pay the extra I/O cost. This restores the original behaviour which was lost when support for register striding was added. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2013-01-03 14:27:15 +00:00
for (i = 0; i < data->chip->num_regs; i++) {
switch (map->format.val_bytes) {
case 1:
data->status_buf[i] = buf8[i];
break;
case 2:
data->status_buf[i] = buf16[i];
break;
case 4:
data->status_buf[i] = buf32[i];
break;
default:
BUG();
return IRQ_NONE;
}
}
} else {
for (i = 0; i < data->chip->num_regs; i++) {
ret = regmap_read(map, chip->status_base +
(i * map->reg_stride
* data->irq_reg_stride),
&data->status_buf[i]);
if (ret != 0) {
dev_err(map->dev,
"Failed to read IRQ status: %d\n",
ret);
if (chip->runtime_pm)
pm_runtime_put(map->dev);
return IRQ_NONE;
}
}
regmap: irq: Factor register read out of the IRQ parsing loop In preparation for adding back support for block reads. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2013-01-03 13:58:33 +00:00
}
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
regmap: irq: Factor register read out of the IRQ parsing loop In preparation for adding back support for block reads. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2013-01-03 13:58:33 +00:00
/*
* Ignore masked IRQs and ack if we need to; we ack early so
* there is no race between handling and acknowleding the
* interrupt. We assume that typically few of the interrupts
* will fire simultaneously so don't worry about overhead from
* doing a write per register.
*/
for (i = 0; i < data->chip->num_regs; i++) {
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
data->status_buf[i] &= ~data->mask_buf[i];
if (data->status_buf[i] && chip->ack_base) {
regmap: fix some error messages to take account of irq_reg_stride A number of places in the code were printing error messages that included the address of a register, but were not calculating the register address in the same way as the access to the register. Use a temporary to solve this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-07-27 19:01:54 +00:00
reg = chip->ack_base +
(i * map->reg_stride * data->irq_reg_stride);
ret = regmap_write(map, reg, data->status_buf[i]);
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
if (ret != 0)
dev_err(map->dev, "Failed to ack 0x%x: %d\n",
regmap: fix some error messages to take account of irq_reg_stride A number of places in the code were printing error messages that included the address of a register, but were not calculating the register address in the same way as the access to the register. Use a temporary to solve this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-07-27 19:01:54 +00:00
reg, ret);
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
}
}
for (i = 0; i < chip->num_irqs; i++) {
regmap: implement register striding regmap_config.reg_stride is introduced. All extant register addresses are a multiple of this value. Users of serial-oriented regmap busses will typically set this to 1. Users of the MMIO regmap bus will typically set this based on the value size of their registers, in bytes, so 4 for a 32-bit register. Throughout the regmap code, actual register addresses are used. Wherever the register address is used to index some array of values, the address is divided by the stride to determine the index, or vice-versa. Error- checking is added to all entry-points for register address data to ensure that register addresses actually satisfy the specified stride. The MMIO bus ensures that the specified stride is large enough for the register size. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-04-09 19:40:24 +00:00
if (data->status_buf[chip->irqs[i].reg_offset /
map->reg_stride] & chip->irqs[i].mask) {
regmap: Convert regmap_irq to use irq_domain This gets us up to date with the recommended current kernel infrastructure and should transparently give us device tree interrupt bindings for any devices using the framework. If an explicit IRQ mapping is passed in then a legacy interrupt range is created, otherwise a simple linear mapping is used. Previously a mapping was mandatory so existing drivers should not be affected. A function regmap_irq_get_virq() is provided to allow drivers to map individual IRQs which should be used in preference to the existing regmap_irq_chip_get_base() which is only valid if a legacy IRQ range is provided. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-05-13 09:59:56 +00:00
handle_nested_irq(irq_find_mapping(data->domain, i));
regmap: Report if we actually handled an interrupt in regmap-irq While the IRQ core doesn't currently support shared threaded interrupts that's no reason for drivers not to do their bit and report IRQ_NONE when they don't get an interrupt. This allows the core spurious/wedget interrupt detection support to do its thing. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-11-28 18:50:39 +00:00
handled = true;
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
}
}
regmap: irq: Enable devices for runtime PM while handling interrupts Some devices need to have a runtime PM reference while handling interrupts to ensure that the register I/O is available. Support this with a flag in the chip. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-07-24 14:41:19 +00:00
if (chip->runtime_pm)
pm_runtime_put(map->dev);
regmap: Report if we actually handled an interrupt in regmap-irq While the IRQ core doesn't currently support shared threaded interrupts that's no reason for drivers not to do their bit and report IRQ_NONE when they don't get an interrupt. This allows the core spurious/wedget interrupt detection support to do its thing. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-11-28 18:50:39 +00:00
if (handled)
return IRQ_HANDLED;
else
return IRQ_NONE;
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
}
regmap: Convert regmap_irq to use irq_domain This gets us up to date with the recommended current kernel infrastructure and should transparently give us device tree interrupt bindings for any devices using the framework. If an explicit IRQ mapping is passed in then a legacy interrupt range is created, otherwise a simple linear mapping is used. Previously a mapping was mandatory so existing drivers should not be affected. A function regmap_irq_get_virq() is provided to allow drivers to map individual IRQs which should be used in preference to the existing regmap_irq_chip_get_base() which is only valid if a legacy IRQ range is provided. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-05-13 09:59:56 +00:00
static int regmap_irq_map(struct irq_domain *h, unsigned int virq,
irq_hw_number_t hw)
{
struct regmap_irq_chip_data *data = h->host_data;
irq_set_chip_data(virq, data);
regmap: no need primary handler for nested irq The primary handler will NOT be called if the interrupt nests into another interrupt thread. Remove it to avoid confusing. Signed-off-by: Yunfan Zhang <yfzhang@marvell.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-09-08 10:53:25 +00:00
irq_set_chip(virq, &data->irq_chip);
regmap: Convert regmap_irq to use irq_domain This gets us up to date with the recommended current kernel infrastructure and should transparently give us device tree interrupt bindings for any devices using the framework. If an explicit IRQ mapping is passed in then a legacy interrupt range is created, otherwise a simple linear mapping is used. Previously a mapping was mandatory so existing drivers should not be affected. A function regmap_irq_get_virq() is provided to allow drivers to map individual IRQs which should be used in preference to the existing regmap_irq_chip_get_base() which is only valid if a legacy IRQ range is provided. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-05-13 09:59:56 +00:00
irq_set_nested_thread(virq, 1);
/* ARM needs us to explicitly flag the IRQ as valid
* and will set them noprobe when we do so. */
#ifdef CONFIG_ARM
set_irq_flags(virq, IRQF_VALID);
#else
irq_set_noprobe(virq);
#endif
return 0;
}
static struct irq_domain_ops regmap_domain_ops = {
.map = regmap_irq_map,
.xlate = irq_domain_xlate_twocell,
};
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
/**
* regmap_add_irq_chip(): Use standard regmap IRQ controller handling
*
* map: The regmap for the device.
* irq: The IRQ the device uses to signal interrupts
* irq_flags: The IRQF_ flags to use for the primary interrupt.
* chip: Configuration for the interrupt controller.
* data: Runtime data structure for the controller, allocated on success
*
* Returns 0 on success or an errno on failure.
*
* In order for this to be efficient the chip really should use a
* register cache. The chip driver is responsible for restoring the
* register values used by the IRQ controller over suspend and resume.
*/
int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
regmap: Constify regmap_irq_chip We should never be modifying it and it lets drivers declare it const. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-05-31 20:01:46 +00:00
int irq_base, const struct regmap_irq_chip *chip,
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
struct regmap_irq_chip_data **data)
{
struct regmap_irq_chip_data *d;
regmap: Convert regmap_irq to use irq_domain This gets us up to date with the recommended current kernel infrastructure and should transparently give us device tree interrupt bindings for any devices using the framework. If an explicit IRQ mapping is passed in then a legacy interrupt range is created, otherwise a simple linear mapping is used. Previously a mapping was mandatory so existing drivers should not be affected. A function regmap_irq_get_virq() is provided to allow drivers to map individual IRQs which should be used in preference to the existing regmap_irq_chip_get_base() which is only valid if a legacy IRQ range is provided. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-05-13 09:59:56 +00:00
int i;
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
int ret = -ENOMEM;
regmap: fix some error messages to take account of irq_reg_stride A number of places in the code were printing error messages that included the address of a register, but were not calculating the register address in the same way as the access to the register. Use a temporary to solve this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-07-27 19:01:54 +00:00
u32 reg;
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
regmap: implement register striding regmap_config.reg_stride is introduced. All extant register addresses are a multiple of this value. Users of serial-oriented regmap busses will typically set this to 1. Users of the MMIO regmap bus will typically set this based on the value size of their registers, in bytes, so 4 for a 32-bit register. Throughout the regmap code, actual register addresses are used. Wherever the register address is used to index some array of values, the address is divided by the stride to determine the index, or vice-versa. Error- checking is added to all entry-points for register address data to ensure that register addresses actually satisfy the specified stride. The MMIO bus ensures that the specified stride is large enough for the register size. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-04-09 19:40:24 +00:00
for (i = 0; i < chip->num_irqs; i++) {
if (chip->irqs[i].reg_offset % map->reg_stride)
return -EINVAL;
if (chip->irqs[i].reg_offset / map->reg_stride >=
chip->num_regs)
return -EINVAL;
}
regmap: Convert regmap_irq to use irq_domain This gets us up to date with the recommended current kernel infrastructure and should transparently give us device tree interrupt bindings for any devices using the framework. If an explicit IRQ mapping is passed in then a legacy interrupt range is created, otherwise a simple linear mapping is used. Previously a mapping was mandatory so existing drivers should not be affected. A function regmap_irq_get_virq() is provided to allow drivers to map individual IRQs which should be used in preference to the existing regmap_irq_chip_get_base() which is only valid if a legacy IRQ range is provided. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-05-13 09:59:56 +00:00
if (irq_base) {
irq_base = irq_alloc_descs(irq_base, 0, chip->num_irqs, 0);
if (irq_base < 0) {
dev_warn(map->dev, "Failed to allocate IRQs: %d\n",
irq_base);
return irq_base;
}
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
}
d = kzalloc(sizeof(*d), GFP_KERNEL);
if (!d)
return -ENOMEM;
regmap: Pass back the allocated regmap IRQ controller data It's needed for freeing and for obtaining the IRQ base later on. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-05-13 10:18:34 +00:00
*data = d;
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
d->status_buf = kzalloc(sizeof(unsigned int) * chip->num_regs,
GFP_KERNEL);
if (!d->status_buf)
goto err_alloc;
d->mask_buf = kzalloc(sizeof(unsigned int) * chip->num_regs,
GFP_KERNEL);
if (!d->mask_buf)
goto err_alloc;
d->mask_buf_def = kzalloc(sizeof(unsigned int) * chip->num_regs,
GFP_KERNEL);
if (!d->mask_buf_def)
goto err_alloc;
regmap: Implement support for wake IRQs Allow chips to provide a bank of registers for controlling the wake state in a similar fashion to the masks and propagate the wake count to the parent interrupt controller. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-06-05 13:34:03 +00:00
if (chip->wake_base) {
d->wake_buf = kzalloc(sizeof(unsigned int) * chip->num_regs,
GFP_KERNEL);
if (!d->wake_buf)
goto err_alloc;
}
regmap: store irq_chip inside regmap_irq_chip_data This will allow later patches to adjust portions of the irq_chip individually for each regmap_irq_chip that is created. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-08-01 17:40:47 +00:00
d->irq_chip = regmap_irq_chip;
regmap: name irq_chip based on regmap_irq_chip's name This is intended to give each irq_chip a useful name, rather than hard- coding them all as "regmap". Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-08-01 17:40:48 +00:00
d->irq_chip.name = chip->name;
regmap: Implement support for wake IRQs Allow chips to provide a bank of registers for controlling the wake state in a similar fashion to the masks and propagate the wake count to the parent interrupt controller. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-06-05 13:34:03 +00:00
d->irq = irq;
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
d->map = map;
d->chip = chip;
d->irq_base = irq_base;
regmap: add support for non contiguous status to regmap-irq In some chips the IRQ status registers are not contiguous in the register map but spaced at even spaces. This is an easy case to handle with minor changes. It is assume for this purpose that the stride for status is equal to the stride for mask/ack registers as well. Signed-off-by: Graeme Gregory <gg@slimlogic.co.uk> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-05-14 13:40:43 +00:00
if (chip->irq_reg_stride)
d->irq_reg_stride = chip->irq_reg_stride;
else
d->irq_reg_stride = 1;
regmap: irq: Use a bulk read for interrupt status where possible If the interrupt status registers are a single block of registers and the chip supports bulk reads then do a single bulk read rather than pay the extra I/O cost. This restores the original behaviour which was lost when support for register striding was added. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2013-01-03 14:27:15 +00:00
if (!map->use_single_rw && map->reg_stride == 1 &&
d->irq_reg_stride == 1) {
d->status_reg_buf = kmalloc(map->format.val_bytes *
chip->num_regs, GFP_KERNEL);
if (!d->status_reg_buf)
goto err_alloc;
}
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
mutex_init(&d->lock);
for (i = 0; i < chip->num_irqs; i++)
regmap: implement register striding regmap_config.reg_stride is introduced. All extant register addresses are a multiple of this value. Users of serial-oriented regmap busses will typically set this to 1. Users of the MMIO regmap bus will typically set this based on the value size of their registers, in bytes, so 4 for a 32-bit register. Throughout the regmap code, actual register addresses are used. Wherever the register address is used to index some array of values, the address is divided by the stride to determine the index, or vice-versa. Error- checking is added to all entry-points for register address data to ensure that register addresses actually satisfy the specified stride. The MMIO bus ensures that the specified stride is large enough for the register size. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-04-09 19:40:24 +00:00
d->mask_buf_def[chip->irqs[i].reg_offset / map->reg_stride]
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
|= chip->irqs[i].mask;
/* Mask all the interrupts by default */
for (i = 0; i < chip->num_regs; i++) {
d->mask_buf[i] = d->mask_buf_def[i];
regmap: fix some error messages to take account of irq_reg_stride A number of places in the code were printing error messages that included the address of a register, but were not calculating the register address in the same way as the access to the register. Use a temporary to solve this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-07-27 19:01:54 +00:00
reg = chip->mask_base +
(i * map->reg_stride * d->irq_reg_stride);
regmap: irq: Add mask invert flag for enable register Currently, regmap will write 1 to mask_base to mask an interrupt and write 0 to unmask it. But some chips do not have an interrupt mask register, and only have interrupt enable register. Then we should write 0 to disable interrupt and 1 to enable. So add an mask_invert flag to handle this. If it is not set, behavior is same as previous. If set it to 1, the mask value will be inverted before written to mask_base Signed-off-by: Xiaofan Tian <tianxf@marvell.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-08-30 09:03:35 +00:00
if (chip->mask_invert)
ret = regmap_update_bits(map, reg,
d->mask_buf[i], ~d->mask_buf[i]);
else
ret = regmap_update_bits(map, reg,
regmap: irq: Only update mask bits when doing initial mask Don't write the full register, it's possible there's bits other than the masks in the same register which we shouldn't be changing. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Tested-by: Stephen Warren <swarren@wwwdotorg.org>
2012-08-01 19:29:14 +00:00
d->mask_buf[i], d->mask_buf[i]);
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
if (ret != 0) {
dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
regmap: fix some error messages to take account of irq_reg_stride A number of places in the code were printing error messages that included the address of a register, but were not calculating the register address in the same way as the access to the register. Use a temporary to solve this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-07-27 19:01:54 +00:00
reg, ret);
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
goto err_alloc;
}
}
regmap: irq: initialize all irqs to wake disabled The kerneldoc for irq_set_irq_wake() says: Enable/disable power management wakeup mode, which is disabled by default. regmap_irq_set_wake() clears bits to enable wake for an interrupt, and sets bits to disable wake. Hence, we should set all bits in wake_buf initially, to mirror the expected disabled state. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-08-01 19:57:24 +00:00
/* Wake is disabled by default */
if (d->wake_buf) {
for (i = 0; i < chip->num_regs; i++) {
d->wake_buf[i] = d->mask_buf_def[i];
reg = chip->wake_base +
(i * map->reg_stride * d->irq_reg_stride);
regmap: irq: Support wake IRQ mask inversion Support devices which have an enable rather than mask register for wake sources. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2013-01-04 16:35:07 +00:00
if (chip->wake_invert)
ret = regmap_update_bits(map, reg,
d->mask_buf_def[i],
0);
else
ret = regmap_update_bits(map, reg,
d->mask_buf_def[i],
d->wake_buf[i]);
regmap: irq: initialize all irqs to wake disabled The kerneldoc for irq_set_irq_wake() says: Enable/disable power management wakeup mode, which is disabled by default. regmap_irq_set_wake() clears bits to enable wake for an interrupt, and sets bits to disable wake. Hence, we should set all bits in wake_buf initially, to mirror the expected disabled state. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-08-01 19:57:24 +00:00
if (ret != 0) {
dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
reg, ret);
goto err_alloc;
}
}
}
regmap: Convert regmap_irq to use irq_domain This gets us up to date with the recommended current kernel infrastructure and should transparently give us device tree interrupt bindings for any devices using the framework. If an explicit IRQ mapping is passed in then a legacy interrupt range is created, otherwise a simple linear mapping is used. Previously a mapping was mandatory so existing drivers should not be affected. A function regmap_irq_get_virq() is provided to allow drivers to map individual IRQs which should be used in preference to the existing regmap_irq_chip_get_base() which is only valid if a legacy IRQ range is provided. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-05-13 09:59:56 +00:00
if (irq_base)
d->domain = irq_domain_add_legacy(map->dev->of_node,
chip->num_irqs, irq_base, 0,
&regmap_domain_ops, d);
else
d->domain = irq_domain_add_linear(map->dev->of_node,
chip->num_irqs,
&regmap_domain_ops, d);
if (!d->domain) {
dev_err(map->dev, "Failed to create IRQ domain\n");
ret = -ENOMEM;
goto err_alloc;
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
}
ret = request_threaded_irq(irq, NULL, regmap_irq_thread, irq_flags,
chip->name, d);
if (ret != 0) {
regmap: irq: Clarify error message when we fail to request primary IRQ Display the name for the chip rather than just the primary IRQ so it is clearer what exactly has failed. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2013-03-19 10:45:04 +00:00
dev_err(map->dev, "Failed to request IRQ %d for %s: %d\n",
irq, chip->name, ret);
regmap: Convert regmap_irq to use irq_domain This gets us up to date with the recommended current kernel infrastructure and should transparently give us device tree interrupt bindings for any devices using the framework. If an explicit IRQ mapping is passed in then a legacy interrupt range is created, otherwise a simple linear mapping is used. Previously a mapping was mandatory so existing drivers should not be affected. A function regmap_irq_get_virq() is provided to allow drivers to map individual IRQs which should be used in preference to the existing regmap_irq_chip_get_base() which is only valid if a legacy IRQ range is provided. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-05-13 09:59:56 +00:00
goto err_domain;
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
}
return 0;
regmap: Convert regmap_irq to use irq_domain This gets us up to date with the recommended current kernel infrastructure and should transparently give us device tree interrupt bindings for any devices using the framework. If an explicit IRQ mapping is passed in then a legacy interrupt range is created, otherwise a simple linear mapping is used. Previously a mapping was mandatory so existing drivers should not be affected. A function regmap_irq_get_virq() is provided to allow drivers to map individual IRQs which should be used in preference to the existing regmap_irq_chip_get_base() which is only valid if a legacy IRQ range is provided. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-05-13 09:59:56 +00:00
err_domain:
/* Should really dispose of the domain but... */
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
err_alloc:
regmap: Implement support for wake IRQs Allow chips to provide a bank of registers for controlling the wake state in a similar fashion to the masks and propagate the wake count to the parent interrupt controller. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-06-05 13:34:03 +00:00
kfree(d->wake_buf);
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
kfree(d->mask_buf_def);
kfree(d->mask_buf);
kfree(d->status_buf);
regmap: irq: Use a bulk read for interrupt status where possible If the interrupt status registers are a single block of registers and the chip supports bulk reads then do a single bulk read rather than pay the extra I/O cost. This restores the original behaviour which was lost when support for register striding was added. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2013-01-03 14:27:15 +00:00
kfree(d->status_reg_buf);
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
kfree(d);
return ret;
}
EXPORT_SYMBOL_GPL(regmap_add_irq_chip);
/**
* regmap_del_irq_chip(): Stop interrupt handling for a regmap IRQ chip
*
* @irq: Primary IRQ for the device
* @d: regmap_irq_chip_data allocated by regmap_add_irq_chip()
*/
void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *d)
{
if (!d)
return;
free_irq(irq, d);
regmap: Convert regmap_irq to use irq_domain This gets us up to date with the recommended current kernel infrastructure and should transparently give us device tree interrupt bindings for any devices using the framework. If an explicit IRQ mapping is passed in then a legacy interrupt range is created, otherwise a simple linear mapping is used. Previously a mapping was mandatory so existing drivers should not be affected. A function regmap_irq_get_virq() is provided to allow drivers to map individual IRQs which should be used in preference to the existing regmap_irq_chip_get_base() which is only valid if a legacy IRQ range is provided. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-05-13 09:59:56 +00:00
/* We should unmap the domain but... */
regmap: Implement support for wake IRQs Allow chips to provide a bank of registers for controlling the wake state in a similar fashion to the masks and propagate the wake count to the parent interrupt controller. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-06-05 13:34:03 +00:00
kfree(d->wake_buf);
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
kfree(d->mask_buf_def);
kfree(d->mask_buf);
regmap: irq: Use a bulk read for interrupt status where possible If the interrupt status registers are a single block of registers and the chip supports bulk reads then do a single bulk read rather than pay the extra I/O cost. This restores the original behaviour which was lost when support for register striding was added. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2013-01-03 14:27:15 +00:00
kfree(d->status_reg_buf);
regmap: Add a reusable irq_chip for regmap based interrupt controllers There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-10-28 21:50:49 +00:00
kfree(d->status_buf);
kfree(d);
}
EXPORT_SYMBOL_GPL(regmap_del_irq_chip);
regmap: Add irq_base accessor to regmap_irq Allows devices to discover their own interrupt without having to remember it themselves. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-12-05 16:10:15 +00:00
/**
* regmap_irq_chip_get_base(): Retrieve interrupt base for a regmap IRQ chip
*
* Useful for drivers to request their own IRQs.
*
* @data: regmap_irq controller to operate on.
*/
int regmap_irq_chip_get_base(struct regmap_irq_chip_data *data)
{
regmap: Convert regmap_irq to use irq_domain This gets us up to date with the recommended current kernel infrastructure and should transparently give us device tree interrupt bindings for any devices using the framework. If an explicit IRQ mapping is passed in then a legacy interrupt range is created, otherwise a simple linear mapping is used. Previously a mapping was mandatory so existing drivers should not be affected. A function regmap_irq_get_virq() is provided to allow drivers to map individual IRQs which should be used in preference to the existing regmap_irq_chip_get_base() which is only valid if a legacy IRQ range is provided. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-05-13 09:59:56 +00:00
WARN_ON(!data->irq_base);
regmap: Add irq_base accessor to regmap_irq Allows devices to discover their own interrupt without having to remember it themselves. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2011-12-05 16:10:15 +00:00
return data->irq_base;
}
EXPORT_SYMBOL_GPL(regmap_irq_chip_get_base);
regmap: Convert regmap_irq to use irq_domain This gets us up to date with the recommended current kernel infrastructure and should transparently give us device tree interrupt bindings for any devices using the framework. If an explicit IRQ mapping is passed in then a legacy interrupt range is created, otherwise a simple linear mapping is used. Previously a mapping was mandatory so existing drivers should not be affected. A function regmap_irq_get_virq() is provided to allow drivers to map individual IRQs which should be used in preference to the existing regmap_irq_chip_get_base() which is only valid if a legacy IRQ range is provided. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-05-13 09:59:56 +00:00
/**
* regmap_irq_get_virq(): Map an interrupt on a chip to a virtual IRQ
*
* Useful for drivers to request their own IRQs.
*
* @data: regmap_irq controller to operate on.
* @irq: index of the interrupt requested in the chip IRQs
*/
int regmap_irq_get_virq(struct regmap_irq_chip_data *data, int irq)
{
regmap: Don't try to map non-existant IRQs If the driver supplied an empty entry in the array of IRQs then return an error rather than trying to do the mapping. This is intended for use with handling chip variants and similar situations. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-06-05 13:29:36 +00:00
/* Handle holes in the IRQ list */
if (!data->chip->irqs[irq].mask)
return -EINVAL;
regmap: Convert regmap_irq to use irq_domain This gets us up to date with the recommended current kernel infrastructure and should transparently give us device tree interrupt bindings for any devices using the framework. If an explicit IRQ mapping is passed in then a legacy interrupt range is created, otherwise a simple linear mapping is used. Previously a mapping was mandatory so existing drivers should not be affected. A function regmap_irq_get_virq() is provided to allow drivers to map individual IRQs which should be used in preference to the existing regmap_irq_chip_get_base() which is only valid if a legacy IRQ range is provided. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-05-13 09:59:56 +00:00
return irq_create_mapping(data->domain, irq);
}
EXPORT_SYMBOL_GPL(regmap_irq_get_virq);
regmap: irq: Allow users to retrieve the irq_domain This is useful for integration with other subsystems, especially MFD, and provides an alternative API for users that request their own IRQs. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-08-20 20:45:05 +00:00
/**
* regmap_irq_get_domain(): Retrieve the irq_domain for the chip
*
* Useful for drivers to request their own IRQs and for integration
* with subsystems. For ease of integration NULL is accepted as a
* domain, allowing devices to just call this even if no domain is
* allocated.
*
* @data: regmap_irq controller to operate on.
*/
struct irq_domain *regmap_irq_get_domain(struct regmap_irq_chip_data *data)
{
if (data)
return data->domain;
else
return NULL;
}
EXPORT_SYMBOL_GPL(regmap_irq_get_domain);
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