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Merge "qcom: clk: Configure wakeup cycles and sleep cycles for gmem clock"

This commit is contained in:
Linux Build Service Account 2015-04-30 23:29:25 -07:00 committed by Gerrit - the friendly Code Review server
parent 143c8f69e6 41d98673a5
commit a14ab987e5
3 changed files with 53 additions and 4 deletions
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8
arch/arm/boot/dts/qcom/msm8939-v3.0.dtsi
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@ -461,3 +461,11 @@
&clock_gcc {
compatible = "qcom,gcc-8936-v3";
};
&gdsc_oxili_gx {
clock-names = "core_root_clk", "gmem_clk";
clocks = <&clock_gcc clk_gfx3d_clk_src>,
<&clock_gcc clk_gcc_oxili_gmem_gate_clk>;
qcom,enable-root-clk;
status = "okay";
};

48
drivers/clk/qcom/clock-gcc-8936.c
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@ -272,6 +272,7 @@ static void __iomem *virt_dbgbase;
#define CAMSS_TOP_AHB_CMD_RCGR 0x5A000
#define BIMC_GFX_CBCR 0x31024
#define BIMC_GPU_CBCR 0x31040
#define GCC_SPARE3_REG 0x7E004
#define APCS_CCI_PLL_MODE 0x00000
#define APCS_CCI_PLL_L_VAL 0x00004
@ -297,6 +298,9 @@ static void __iomem *virt_dbgbase;
#define APCS_C1_PLL_CONFIG_CTL 0x00014
#define APCS_C1_PLL_STATUS 0x0001C
#define CLKFLAG_WAKEUP_CYCLES 0x0
#define CLKFLAG_SLEEP_CYCLES 0x0
/* Mux source select values */
#define gcc_xo_source_val 0
#define xo_a_clk_source_val 0
@ -2326,6 +2330,19 @@ static struct branch_clk gcc_oxili_gmem_clk = {
},
};
static struct gate_clk gcc_oxili_gmem_gate_clk = {
.en_reg = OXILI_GMEM_CBCR,
.en_mask = BIT(0),
.delay_us = 50,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_oxili_gmem_gate_clk",
.parent = &gfx3d_clk_src.c,
.ops = &clk_ops_gate,
CLK_INIT(gcc_oxili_gmem_gate_clk.c),
},
};
static struct local_vote_clk gcc_apss_tcu_clk;
static struct branch_clk gcc_bimc_gfx_clk = {
.cbcr_reg = BIMC_GFX_CBCR,
@ -3254,7 +3271,6 @@ static struct clk_lookup msm_clocks_lookup[] = {
CLK_LIST(gcc_camss_vfe0_clk),
CLK_LIST(gcc_camss_vfe_ahb_clk),
CLK_LIST(gcc_camss_vfe_axi_clk),
CLK_LIST(gcc_oxili_gmem_clk),
CLK_LIST(gcc_gp1_clk),
CLK_LIST(gcc_gp2_clk),
CLK_LIST(gcc_gp3_clk),
@ -3297,6 +3313,14 @@ static struct clk_lookup msm_clocks_lookup[] = {
CLK_LIST(crypto_clk_src),
};
static struct clk_lookup msm_clocks_lookup_v1[] = {
CLK_LIST(gcc_oxili_gmem_clk),
};
static struct clk_lookup msm_clocks_lookup_v3[] = {
CLK_LIST(gcc_oxili_gmem_gate_clk),
};
/* Please note that the order of reg-names is important */
static int get_memory(struct platform_device *pdev)
{
@ -3418,12 +3442,28 @@ static int msm_gcc_probe(struct platform_device *pdev)
if (ret)
return ret;
if (compat_bin) {
ret = of_msm_clock_register(pdev->dev.of_node,
msm_clocks_lookup_v3,
ARRAY_SIZE(msm_clocks_lookup_v3));
regval = readl_relaxed(GCC_REG_BASE(OXILI_GMEM_CBCR));
regval ^= 0xFF0;
regval |= CLKFLAG_WAKEUP_CYCLES << 8;
regval |= CLKFLAG_SLEEP_CYCLES << 4;
writel_relaxed(regval, GCC_REG_BASE(OXILI_GMEM_CBCR));
/* Enable GMEM HW Dynamic */
writel_relaxed(regval, GCC_REG_BASE(GCC_SPARE3_REG));
} else
ret = of_msm_clock_register(pdev->dev.of_node,
msm_clocks_lookup_v1,
ARRAY_SIZE(msm_clocks_lookup_v1));
if (ret)
return ret;
clk_set_rate(&apss_ahb_clk_src.c, 19200000);
clk_prepare_enable(&apss_ahb_clk_src.c);
if (compat_bin)
gcc_bimc_gfx_clk.c.depends = NULL;
dev_info(&pdev->dev, "Registered GCC clocks\n");
return 0;

1
include/dt-bindings/clock/msm-clocks-8936.h
View File

@ -154,6 +154,7 @@
#define clk_gcc_camss_vfe_ahb_clk 0x4050f47a
#define clk_gcc_camss_vfe_axi_clk 0x77fe2384
#define clk_gcc_oxili_gmem_clk 0x5620913a
#define clk_gcc_oxili_gmem_gate_clk 0xd179f583
#define clk_gcc_gp1_clk 0x057f7b69
#define clk_gcc_gp2_clk 0x9bf83ffd
#define clk_gcc_gp3_clk 0xec6539ee