Merge "qcom: clk: Configure wakeup cycles and sleep cycles for gmem clock"
This commit is contained in:
commit
a14ab987e5
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@ -461,3 +461,11 @@
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&clock_gcc {
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&clock_gcc {
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compatible = "qcom,gcc-8936-v3";
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compatible = "qcom,gcc-8936-v3";
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};
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};
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&gdsc_oxili_gx {
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clock-names = "core_root_clk", "gmem_clk";
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clocks = <&clock_gcc clk_gfx3d_clk_src>,
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<&clock_gcc clk_gcc_oxili_gmem_gate_clk>;
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qcom,enable-root-clk;
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status = "okay";
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};
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@ -272,6 +272,7 @@ static void __iomem *virt_dbgbase;
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#define CAMSS_TOP_AHB_CMD_RCGR 0x5A000
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#define CAMSS_TOP_AHB_CMD_RCGR 0x5A000
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#define BIMC_GFX_CBCR 0x31024
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#define BIMC_GFX_CBCR 0x31024
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#define BIMC_GPU_CBCR 0x31040
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#define BIMC_GPU_CBCR 0x31040
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#define GCC_SPARE3_REG 0x7E004
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#define APCS_CCI_PLL_MODE 0x00000
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#define APCS_CCI_PLL_MODE 0x00000
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#define APCS_CCI_PLL_L_VAL 0x00004
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#define APCS_CCI_PLL_L_VAL 0x00004
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@ -297,6 +298,9 @@ static void __iomem *virt_dbgbase;
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#define APCS_C1_PLL_CONFIG_CTL 0x00014
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#define APCS_C1_PLL_CONFIG_CTL 0x00014
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#define APCS_C1_PLL_STATUS 0x0001C
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#define APCS_C1_PLL_STATUS 0x0001C
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#define CLKFLAG_WAKEUP_CYCLES 0x0
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#define CLKFLAG_SLEEP_CYCLES 0x0
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/* Mux source select values */
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/* Mux source select values */
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#define gcc_xo_source_val 0
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#define gcc_xo_source_val 0
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#define xo_a_clk_source_val 0
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#define xo_a_clk_source_val 0
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@ -2326,6 +2330,19 @@ static struct branch_clk gcc_oxili_gmem_clk = {
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},
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},
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};
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};
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static struct gate_clk gcc_oxili_gmem_gate_clk = {
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.en_reg = OXILI_GMEM_CBCR,
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.en_mask = BIT(0),
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.delay_us = 50,
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.base = &virt_bases[GCC_BASE],
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.c = {
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.dbg_name = "gcc_oxili_gmem_gate_clk",
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.parent = &gfx3d_clk_src.c,
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.ops = &clk_ops_gate,
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CLK_INIT(gcc_oxili_gmem_gate_clk.c),
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},
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};
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static struct local_vote_clk gcc_apss_tcu_clk;
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static struct local_vote_clk gcc_apss_tcu_clk;
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static struct branch_clk gcc_bimc_gfx_clk = {
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static struct branch_clk gcc_bimc_gfx_clk = {
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.cbcr_reg = BIMC_GFX_CBCR,
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.cbcr_reg = BIMC_GFX_CBCR,
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@ -3254,7 +3271,6 @@ static struct clk_lookup msm_clocks_lookup[] = {
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CLK_LIST(gcc_camss_vfe0_clk),
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CLK_LIST(gcc_camss_vfe0_clk),
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CLK_LIST(gcc_camss_vfe_ahb_clk),
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CLK_LIST(gcc_camss_vfe_ahb_clk),
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CLK_LIST(gcc_camss_vfe_axi_clk),
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CLK_LIST(gcc_camss_vfe_axi_clk),
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CLK_LIST(gcc_oxili_gmem_clk),
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CLK_LIST(gcc_gp1_clk),
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CLK_LIST(gcc_gp1_clk),
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CLK_LIST(gcc_gp2_clk),
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CLK_LIST(gcc_gp2_clk),
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CLK_LIST(gcc_gp3_clk),
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CLK_LIST(gcc_gp3_clk),
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@ -3297,6 +3313,14 @@ static struct clk_lookup msm_clocks_lookup[] = {
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CLK_LIST(crypto_clk_src),
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CLK_LIST(crypto_clk_src),
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};
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};
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static struct clk_lookup msm_clocks_lookup_v1[] = {
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CLK_LIST(gcc_oxili_gmem_clk),
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};
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static struct clk_lookup msm_clocks_lookup_v3[] = {
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CLK_LIST(gcc_oxili_gmem_gate_clk),
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};
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/* Please note that the order of reg-names is important */
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/* Please note that the order of reg-names is important */
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static int get_memory(struct platform_device *pdev)
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static int get_memory(struct platform_device *pdev)
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{
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{
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@ -3418,12 +3442,28 @@ static int msm_gcc_probe(struct platform_device *pdev)
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if (ret)
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if (ret)
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return ret;
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return ret;
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if (compat_bin) {
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ret = of_msm_clock_register(pdev->dev.of_node,
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msm_clocks_lookup_v3,
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ARRAY_SIZE(msm_clocks_lookup_v3));
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regval = readl_relaxed(GCC_REG_BASE(OXILI_GMEM_CBCR));
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regval ^= 0xFF0;
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regval |= CLKFLAG_WAKEUP_CYCLES << 8;
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regval |= CLKFLAG_SLEEP_CYCLES << 4;
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writel_relaxed(regval, GCC_REG_BASE(OXILI_GMEM_CBCR));
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/* Enable GMEM HW Dynamic */
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writel_relaxed(regval, GCC_REG_BASE(GCC_SPARE3_REG));
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} else
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ret = of_msm_clock_register(pdev->dev.of_node,
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msm_clocks_lookup_v1,
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ARRAY_SIZE(msm_clocks_lookup_v1));
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if (ret)
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return ret;
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clk_set_rate(&apss_ahb_clk_src.c, 19200000);
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clk_set_rate(&apss_ahb_clk_src.c, 19200000);
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clk_prepare_enable(&apss_ahb_clk_src.c);
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clk_prepare_enable(&apss_ahb_clk_src.c);
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if (compat_bin)
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gcc_bimc_gfx_clk.c.depends = NULL;
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dev_info(&pdev->dev, "Registered GCC clocks\n");
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dev_info(&pdev->dev, "Registered GCC clocks\n");
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return 0;
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return 0;
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@ -154,6 +154,7 @@
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#define clk_gcc_camss_vfe_ahb_clk 0x4050f47a
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#define clk_gcc_camss_vfe_ahb_clk 0x4050f47a
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#define clk_gcc_camss_vfe_axi_clk 0x77fe2384
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#define clk_gcc_camss_vfe_axi_clk 0x77fe2384
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#define clk_gcc_oxili_gmem_clk 0x5620913a
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#define clk_gcc_oxili_gmem_clk 0x5620913a
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#define clk_gcc_oxili_gmem_gate_clk 0xd179f583
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#define clk_gcc_gp1_clk 0x057f7b69
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#define clk_gcc_gp1_clk 0x057f7b69
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#define clk_gcc_gp2_clk 0x9bf83ffd
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#define clk_gcc_gp2_clk 0x9bf83ffd
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#define clk_gcc_gp3_clk 0xec6539ee
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#define clk_gcc_gp3_clk 0xec6539ee
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