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ASoC: wcd9335: Update SIDO buck register sequence for WCD9335 v2.0
Set current(IRef) and voltage(VRef) references to external and use supply from RCO (RC Oscillator) bandgap. Change-Id: I9c0d608011e20670aafaa343d7c11c17129b5704 Signed-off-by: Sudheer Papothi <spapothi@codeaurora.org>
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parent
4fd6901dc6
commit
ac9cbc4bfa
3 changed files with 38 additions and 6 deletions
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@ -660,6 +660,20 @@ struct tasha_priv {
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static enum codec_variant codec_ver;
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static void tasha_enable_sido_buck(struct snd_soc_codec *codec)
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{
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struct tasha_priv *tasha = snd_soc_codec_get_drvdata(codec);
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snd_soc_update_bits(codec, WCD9335_ANA_RCO, 0x80, 0x80);
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snd_soc_update_bits(codec, WCD9335_ANA_BUCK_CTL, 0x02, 0x02);
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/* 100us sleep needed after IREF settings */
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usleep_range(100, 110);
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snd_soc_update_bits(codec, WCD9335_ANA_BUCK_CTL, 0x04, 0x04);
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/* 100us sleep needed after VREF settings */
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usleep_range(100, 110);
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tasha->resmgr->sido_input_src = SIDO_SOURCE_RCO_BG;
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}
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int tasha_enable_efuse_sensing(struct snd_soc_codec *codec)
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{
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struct tasha_priv *priv = snd_soc_codec_get_drvdata(codec);
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@ -679,6 +693,9 @@ int tasha_enable_efuse_sensing(struct snd_soc_codec *codec)
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if (!(snd_soc_read(codec, WCD9335_CHIP_TIER_CTRL_EFUSE_STATUS) & 0x01))
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WARN(1, "%s: Efuse sense is not complete\n", __func__);
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if (TASHA_IS_2_0(priv->wcd9xxx->version))
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tasha_enable_sido_buck(codec);
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tasha_cdc_mclk_enable(codec, false, false);
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return 0;
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@ -9871,6 +9888,8 @@ static int tasha_codec_probe(struct snd_soc_codec *codec)
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0x03, 0x01);
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tasha_codec_init_reg(codec);
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tasha_enable_efuse_sensing(codec);
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pdata = dev_get_platdata(codec->dev->parent);
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ret = tasha_handle_pdata(tasha, pdata);
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if (IS_ERR_VALUE(ret)) {
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@ -264,8 +264,10 @@ static int wcd_resmgr_enable_clk_rco(struct wcd9xxx_resmgr_v2 *resmgr)
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} else if ((resmgr->clk_rco_users == 1) &&
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(resmgr->clk_mclk_users)) {
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/* RCO Enable */
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wcd_resmgr_codec_reg_update_bits(resmgr, WCD9335_ANA_RCO,
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0x80, 0x80);
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if (resmgr->sido_input_src == SIDO_SOURCE_INTERNAL)
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wcd_resmgr_codec_reg_update_bits(resmgr,
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WCD9335_ANA_RCO,
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0x80, 0x80);
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/*
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* 20us required after RCO BG is enabled as per HW
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* requirements
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@ -318,16 +320,20 @@ static int wcd_resmgr_disable_clk_rco(struct wcd9xxx_resmgr_v2 *resmgr)
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0x04, 0x00);
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wcd_resmgr_codec_reg_update_bits(resmgr, WCD9335_ANA_RCO,
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0x40, 0x00);
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wcd_resmgr_codec_reg_update_bits(resmgr, WCD9335_ANA_RCO,
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0x80, 0x00);
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if (resmgr->sido_input_src == SIDO_SOURCE_INTERNAL)
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wcd_resmgr_codec_reg_update_bits(resmgr,
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WCD9335_ANA_RCO,
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0x80, 0x00);
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resmgr->clk_type = WCD_CLK_OFF;
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} else if ((resmgr->clk_rco_users == 0) &&
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(resmgr->clk_mclk_users)) {
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/* Disable RCO while MCLK is ON */
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wcd_resmgr_codec_reg_update_bits(resmgr, WCD9335_ANA_RCO,
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0x40, 0x00);
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wcd_resmgr_codec_reg_update_bits(resmgr, WCD9335_ANA_RCO,
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0x80, 0x00);
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if (resmgr->sido_input_src == SIDO_SOURCE_INTERNAL)
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wcd_resmgr_codec_reg_update_bits(resmgr,
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WCD9335_ANA_RCO,
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0x80, 0x00);
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}
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pr_debug("%s: rco clk users: %d, clk_type: %s\n", __func__,
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resmgr->clk_rco_users,
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@ -424,6 +430,7 @@ struct wcd9xxx_resmgr_v2 *wcd_resmgr_init(
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resmgr->master_bias_users = 0;
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resmgr->codec = codec;
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resmgr->core_res = core_res;
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resmgr->sido_input_src = SIDO_SOURCE_INTERNAL;
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return resmgr;
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}
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@ -22,6 +22,11 @@ enum wcd_clock_type {
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WCD_CLK_MCLK,
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};
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enum {
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SIDO_SOURCE_INTERNAL,
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SIDO_SOURCE_RCO_BG,
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};
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struct wcd_resmgr_cb {
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int (*cdc_rco_ctrl)(struct snd_soc_codec *, bool);
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};
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@ -40,6 +45,7 @@ struct wcd9xxx_resmgr_v2 {
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enum wcd_clock_type clk_type;
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const struct wcd_resmgr_cb *resmgr_cb;
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int sido_input_src;
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};
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#define WCD9XXX_V2_BG_CLK_LOCK(resmgr) \
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