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ARM: dts: msm: Add qcom,clk-dis-wait-val value for MSM8976

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Along with clk-dis-wait-val to 0x5, we need to sleep value of
OXILI_GFX3D_CBCR to be 0x0.

Change-Id: I8732a0d050d7f7ff2fba0d7faec12c38767861aa
Signed-off-by: Taniya Das <tdas@codeaurora.org>
This commit is contained in:
Taniya Das 2015-07-24 15:01:55 +05:30 committed by Gerrit - the friendly Code Review server
parent 5b0ce1c3bd
commit bb4a3b5333
2 changed files with 7 additions and 0 deletions
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1
arch/arm/boot/dts/qcom/msm8976.dtsi
View file

@ -2666,6 +2666,7 @@
clocks =<&clock_gcc_gfx clk_gfx3d_clk_src>,
<&clock_gcc_gfx clk_gcc_oxili_gmem_clk>;
qcom,enable-root-clk;
qcom,clk-dis-wait-val = <0x5>;
parent-supply = <&gfx_vreg_corner>;
status = "okay";
};

6
drivers/clk/qcom/clock-gcc-8976.c
View file

@ -3967,6 +3967,12 @@ static int msm_gcc_gfx_probe(struct platform_device *pdev)
regval &= ~BIT(0);
writel_relaxed(regval, GCC_REG_BASE(GX_DOMAIN_MISC));
/* Configure Sleep and Wakeup cycles for OXILI clock */
regval = readl_relaxed(GCC_REG_BASE(OXILI_GFX3D_CBCR));
regval &= ~0xF0;
regval |= CLKFLAG_SLEEP_CYCLES << 4;
writel_relaxed(regval, GCC_REG_BASE(OXILI_GFX3D_CBCR));
dev_info(&pdev->dev, "Registered GCC GFX clocks.\n");
populate_gpu_opp_table(pdev);