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msm: pcie: add support to enable clk power management for EP 

Add support to enable the clock power management for the
endpoint.

Change-Id: I02bebfeb5d32eb8e1f75ee5feb4c4fff956ece66
Signed-off-by: Tony Truong <truong@codeaurora.org>
This commit is contained in:
Tony Truong 2015-01-28 18:20:25 -08:00
parent cde5f8905c
commit ee0bb004ee
2 changed files with 28 additions and 0 deletions
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2
Documentation/devicetree/bindings/pci/msm_pcie.txt
View File

@ -57,6 +57,8 @@ Optional Properties:
- qcom,aux-clk-sync: The AUX clock is synchronous to the Core clock to
support L1ss.
- qcom,common-clk-en: Enables the common clock configuration for the endpoint.
- qcom,clk-power-manage-en: Enables the clock power management for the
endpoint.
- qcom,n-fts: The number of fast training sequences sent when the link state
is changed from L0s to L0.
- qcom,ep-wakeirq: The endpoint will issue wake signal when it is up, and the

26
drivers/pci/host/pci-msm.c
View File

@ -494,6 +494,7 @@ struct msm_pcie_dev_t {
bool l1_supported;
bool l1ss_supported;
bool common_clk_en;
bool clk_power_manage_en;
bool aux_clk_sync;
uint32_t n_fts;
bool ext_ref_clk;
@ -1223,6 +1224,8 @@ static void msm_pcie_show_status(struct msm_pcie_dev_t *dev)
dev->l1ss_supported ? "" : "not");
pr_alert("common_clk_en is %d\n",
dev->common_clk_en);
pr_alert("clk_power_manage_en is %d\n",
dev->clk_power_manage_en);
pr_alert("aux_clk_sync is %d\n",
dev->aux_clk_sync);
pr_alert("ext_ref_clk is %d\n",
@ -2788,6 +2791,23 @@ static void msm_pcie_config_link_state(struct msm_pcie_dev_t *dev)
readl_relaxed(dev->conf + ep_link_ctrlstts_offset));
}
if (dev->clk_power_manage_en) {
val = readl_relaxed(dev->conf + ep_link_cap_offset);
if (val & BIT(18)) {
msm_pcie_write_mask(dev->conf + ep_link_ctrlstts_offset,
0, BIT(8));
if (dev->shadow_en)
dev->ep_shadow[0][ep_link_ctrlstts_offset / 4] =
readl_relaxed(dev->conf +
ep_link_ctrlstts_offset);
PCIE_DBG2(dev, "EP's CAP_LINKCTRLSTATUS:0x%x\n",
readl_relaxed(dev->conf +
ep_link_ctrlstts_offset));
}
}
if (dev->l0s_supported) {
msm_pcie_write_mask(dev->dm_core + PCIE20_CAP_LINKCTRLSTATUS,
0, BIT(0));
@ -4491,6 +4511,12 @@ static int msm_pcie_probe(struct platform_device *pdev)
"qcom,common-clk-en");
PCIE_DBG(&msm_pcie_dev[rc_idx], "Common clock is %s enabled.\n",
msm_pcie_dev[rc_idx].common_clk_en ? "" : "not");
msm_pcie_dev[rc_idx].clk_power_manage_en =
of_property_read_bool((&pdev->dev)->of_node,
"qcom,clk-power-manage-en");
PCIE_DBG(&msm_pcie_dev[rc_idx],
"Clock power management is %s enabled.\n",
msm_pcie_dev[rc_idx].clk_power_manage_en ? "" : "not");
msm_pcie_dev[rc_idx].aux_clk_sync =
of_property_read_bool((&pdev->dev)->of_node,
"qcom,aux-clk-sync");