Add driver support to enable scatter-gather feature with TMC configuration.
Scatter gather option for ETR DDR mode supports the use of a table of
locations of 4K blocks of physical memory. Since this memory is not
necessarily contiguous, user can increase the trace buffer size as long as
DDR memory is available.
Default memory option is "contig" for TMC ETR DDR configuration. User can
enable scatter gather feature dynamically.
Change-Id: I74136fb86fe751aa33607d3922dce5d572f0a4a2
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
Based on sg-enable DT entry, enable scatter gather feature
for TMC ETR configuration. Scatter gather feature is not supported
on all targets. sg-enable entry will help to enable this feature
only on those targets which supports this feature.
Change-Id: I66fe50c653ad9646104b9dc0d77a0fa6f82503dd
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
Add device attribute for memory type option with TMC ETR DDR configuration.
This is in preparation for scatter gather feature with TMC ETR
configuration.
Change-Id: If72078f89442e9c58e09392fbced362126dd15e7
Signed-off-by: Sarang Joshi <spjoshi@codeaurora.org>
Add client support to register with the memory dump v2 driver to
take advantage of the new enhanced memory dump format.
Change-Id: I8b05d92b3e9f4d1dcaa6dffec8fe05401d72a7ee
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
General cleanup to avoid global name space clashes. This is in
preparation for the memory dump v2 driver.
Change-Id: I884ff3a06c74166dc0cd9004085ab9b43646ef6a
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Add support for Embedded Trace Macrocell v4 trace architecture
which is required for instruction trace on ARMv8 arctitecture.
Change-Id: Iff24690e3161eb12d6f0e09af0c45f9739c7ca66
Signed-off-by: Aparna Das <adas@codeaurora.org>
When byte counter feature is enabled, if the rate at which we receive IRQs
is so high that userspace is unable to read the data fast enough, we
throw byte counter overflow error message. However these messages can cause
log spew resulting in watchdog bark/bite. Limit byte counter overflow
message spew by using rate limited function.
Change-Id: I714323893330368965f70a137aaef7ef7cd4029d
Signed-off-by: Sarang Joshi <spjoshi@codeaurora.org>
Use pin control framework to configure pin resources for
obtaining TPIU trace via mictor instead of GPIO lib
implementations used earlier. Modify the CoreSight TPIU driver
to implement this change.
Change-Id: Ifc565994214ee7c4f7abb97b4222352becfdf2b4
Signed-off-by: Aparna Das <adas@codeaurora.org>
Change the bam handle data type from u32 to
unsigned long to match sps connect source
and destination.
Change-Id: I55ce477a40e4ab3d1306f8afd1acf491c22874e9
Signed-off-by: Sujeet Kumar <ksujeet@codeaurora.org>
Add support for CoreSight QPDI driver which provides
controlled access to PMIC Debug Interface.
Change-Id: Ia2e6cc4e276923b55f34046a6a422e7533768e72
Signed-off-by: Aparna Das <adas@codeaurora.org>
Dynamically allocate ETR DDR memory so that user can specify
trace buffer size at runtime.
Change-Id: I081b017fa147d7c87789cc504cd9b61b7365c79f
Signed-off-by: Sarang Joshi <spjoshi@codeaurora.org>
As part of moving the headers from mach directory
to a common location compilation issues are arising.
Make the changes which are relevant for USB with
its own header files and also dependent header
files.
Change-Id: Ieef7d04ffdfda249f434e0676fec6da8d8b9cf2c
Signed-off-by: Sujeet Kumar <ksujeet@codeaurora.org>
We call coresight_abort() early in panic pathway to avoid trace buffer
getting cluttered with uninteresting messages; however sometimes it tends
to loose important info such as kernel sending notification to all
peripheral subsystems since it happens after aborting of CoreSight trace.
Add trace event to abort tracing late in kernel panic.
trace_event_kernel_panic and trace_event_kernel_panic_late are mutually
exclusive and can be control using module parameter. With this change user
will be able to choose whether to abort CoreSight trace early or late on
kernel panic.
Change-Id: I84cc299823d929fdf8129c9c728282b32391b7c1
Signed-off-by: Sarang Joshi <spjoshi@codeaurora.org>
Add trace event to control aborting CoreSight trace
dynamically based on module parameter. This will help
user to enable/disable coresight_abort on kernel panic.
Also moved CREATE_TRACE_POINTS to panic.c from fault.c
since panic.c is common and shared between 32 and 64
bit platforms.
Change-Id: I51e4049b07adeca571b1a98cd90ff5f307d1d794
Signed-off-by: Sarang Joshi <spjoshi@codeaurora.org>
Add device attribute to control ETR DDR memory size dynamically
for TMC configuration. This will help users to specify DDR trace
buffer size at runtime.
Change-Id: Ie1edef7f972435193c96dafb8a94fd6cce97ce6c
Signed-off-by: Sarang Joshi <spjoshi@codeaurora.org>
Allow configuring CoreSight funnels required for remote processor ETM
tracing even if QMI server is not available to handle QMI client
requests. This allows enabling ETM trace via other alternatives and
use CoreSight drivers to collect trace data.
Change-Id: I43ba5ba5050af23877ddc53694418c35356bae4f
Signed-off-by: Aparna Das <adas@codeaurora.org>
Architectural changes in the ARM Linux kernel tree mandate
the eventual removal of the mach-* directories. Move the
memory dump driver to drivers/soc/qcom and the memory dump header
to include/soc/qcom to support that removal.
Change-Id: If04f6a4fcd30c864321ac0ff8c6691fc20707cc1
Signed-off-by: Xiaogang Cui <xiaogang@codeaurora.org>
Signed-off-by: Aparna Das <adas@codeaurora.org>
Remove the sps header file from older location as sps
driver and clients need to use new header file from
new location include/linux.
Resolve the warnings/errors from client drivers due to
new sps header changes.
Change-Id: I1cdb87756abf3425a9bb5d8bf89cd1aa03a01716
Signed-off-by: Dipen Parmar <dipenp@codeaurora.org>
Fix compilation errors to support gcc-4.8
There is compilation warnning when use '%d" to print a argument
which type is size_t.
In file included from kernel/include/linux/kernel.h:14:0,
from kernel/drivers/coresight/coresight-tmc.c:13:
kernel/drivers/coresight/coresight-tmc.c: In function 'tmc_read':
kernel/include/linux/dynamic_debug.h:64:16: warning:
format '%d' expects argument of type 'int', but argument 5 has type
'size_t' [-Wformat=] error, forbidden warning: dynamic_debug.h:64
Change format '%d' to '%zu' to fix this compilation error
Change-Id: Ia746033b76df7f06e860031ed8d3e249facbe2b5
Signed-off-by: Xiaogang Cui <xiaogang@codeaurora.org>
The TMC driver now uses dma_alloc_coherent api to allocate contiguous
memory instead of allocate_contiguous_ebi when configured for ETR. This
eliminates the need for EXPORT_COMPAT support in the TMC driver.
Change-Id: I79550d2ff490c02329e4b860b8aa8816d4890d50
Signed-off-by: Aparna Das <adas@codeaurora.org>
Upstream prefers existing drivers be converted to support multiplatform
kernels. This requires drivers to be located in directories that
contain generic functionality instead of specific mach directories.
Move the socinfo driver into drivers/soc/qcom and update the initcall
levels to satisfy dependencies.
Change-Id: If195cd793d84867d371f25136a88f2a7ce239500
Signed-off-by: Xiaocheng Li <lix@codeaurora.org>
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
Add QMI messaging support to communicate with remote processors to
enable or disable ETM on remote processors.
Change-Id: I7018492284f1e5816302189f8c4f918b3ab79a64
Signed-off-by: Aparna Das <adas@codeaurora.org>
Byte counter overflow is computed based on byte counter value during
byte counter start routine. Two different threads running in parallel
can cause synchronization issue where one thread modifies overflow
based on byte counter value and other thread modifies byte counter
value at the same time. Take respective lock before setting byte
counter value.
Change-Id: I923a34bf918abe4d5e3b0d30ed4887a38db6f427
Signed-off-by: Sarang Joshi <spjoshi@codeaurora.org>
This change removes source files from the kernel tree that
were not being used during make. The list of used files
was generated using an annotated make log and was then
compared with new files added since the public release of
kernel version 3.10.00. New files which were added but
not used have been removed from the tree.
A diff was also run to determine the list of files that had
been modified since the release of kernel version 3.10.00.
These files were then scrubbed based on the current kernel
configuration, removing invalid and unused conditionals.
Some files which support planned functionality or are
useful in debugging have been excluded from this reap.
Change-Id: Ia44a224d3cea7bc78dd45e8a8279860d35d4b008
Signed-off-by: Ian Maund <imaund@codeaurora.org>
Rearrange show_trigin and show_trigout function locations to be
consistent with other CoreSight drivers.
Change-Id: Ic877155e49aa9379ba98e8473812b7f0359e8024
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Add support for cti enable and disable functions to allow use
cases that require the ability to control the trigger outputs
independent of the trigger mapping and generation configuration.
Change-Id: Id94809be629bb3939a67e8f6711733810aeb1f37
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Add support for setting and clearing triggers to allow use cases
that require software based trigger setting and clearing
functionality.
Change-Id: I826b238f2cb1050394134030bd0810bbcdeb2662
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Add support for pulse triggering to allow uses cases that require
software based pulse trigger generation.
Change-Id: I1ce8fd40cfd0622364c101f9d9bc8aa4540b0344
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Split cti_verify_bounds into cti_verify_trigger_bound and
cti_verify_channel_bound so that they can be used individually
when required.
Change-Id: Ic1cd6802b0f5f0e7d9d31da73b0817d8f1909c3d
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Add trace event to abort tracing for unhandled aborts such as
data abort and prefetch abort. A common event 'trace_unhandled_abort'
is shared for all unhandled aborts.
Change-Id: I6da9b30c74be48252402188a6f9a7703d21d6276
Signed-off-by: Sarang Joshi <spjoshi@codeaurora.org>
The coresight event module helps abort tracing on user fault
and undefined instruction exceptions. Add module parameter to
control it dynamically.
Change-Id: Iecaa144b99e3786c8c8f570f989f747be12c4fdc
Signed-off-by: Sarang Joshi <spjoshi@codeaurora.org>
If gpio entries are not present in dt file, the resource query
function returns negative value for gpio count. Currently data
type for gpio count is unsigned int which wraps around and gives
positive result for negative value that causes failure while
probing the driver. Modify gpio count data type to integer and
check if it is positive before using it.
Change-Id: I1596f3d1090f5caa70735c66e10f82914ac7ab26
Signed-off-by: Sarang Joshi <spjoshi@codeaurora.org>
Modify function names and messages to be consistent with other
modules. Modify function names starting with control_* to
event_*, abort_control_tracing to event_trace_user_fault and
abort_tracing_undef_instr to event_trace_undef_instr.
Change-Id: Ic6101dc8024b8d10713c162ea93e268ba59eaf8a
Signed-off-by: Sarang Joshi <spjoshi@codeaurora.org>
Fix error checks for byte counter initialization functions that
are called during probe to avoid null pointer accesses.
CRs-Fixed: 562303
Change-Id: I8f7de6fc4b0658cf649e472d12a00ea5733a8b0a
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Add support to switch between various Narrow Interface for Debug and
Trace (NIDnT) modes namely Serial Wire Debug, UART and Trace modes
through SD card interface.
Change-Id: I3d263fe7ec623b0d9c81021d79a69ba5b54ad7e0
Signed-off-by: Aparna Das <adas@codeaurora.org>
Currently the remote processors do not have access to CoreSight debug
and trace framework. Add support for configuring the required CoreSight
components to enable ETM tracing on these processors.
Change-Id: I1a2aa6567f26124124cf1c570575836e62519052
Signed-off-by: Aparna Das <adas@codeaurora.org>
Read cti mappings only when cti is enabled to ensure required cti clock
is enabled.
Change-Id: I7500b44a44c058f37497c2226b8e1b097e734b87
Signed-off-by: Aparna Das <adas@codeaurora.org>
Vote for a fixed clock frequency for TPIU output to SD to
workaround trace data corruption issues across XO shutdown.
Change-Id: Iaa7e822899685c3b5d0cc01dea1090e817e9b129
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
The sdc io regulator is configured and enabled when TPIU trace via sdc
is enabled. Disable this regulator when TPIU trace is disabled.
Change-Id: Ib1dfacb1c4977c74b1796f17f763f8abea583171
Signed-off-by: Aparna Das <adas@codeaurora.org>
During kernel panic, coresight_abort is first called to stop
tracing to the default ETF (circular buffer mode) sink. This is
followed by stopping RTB as part of the panic handler.
Use no log version of readl while dumping ETF in circular buffer
mode to avoid polluting RTB logs with readls responsible for
dumping ETF during kernel panic.
Change-Id: I282516be458c8b38af20cb372803cdff9eb9e8f0
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
The CoreSight TMC driver when configured for ETR requires uncached
memory in RAM to which it routes trace data. In order to allocate
this memory replace existing allocate_contiguous_ebi api with
dma_alloc_coherent api which is the linux standard of allocating
memory.
Change-Id: I59f88009f2abed95fd9b81ea92a7d484b9d6b833
Signed-off-by: Aparna Das <adas@codeaurora.org>
Periodic flushing for ETR to USB uses ETR flush-on-FLUSHIN
external input. Hence, enable flush-on-FLUSHIN by default when
enabling ETR to USB transfers and work around the manual flush
failure by skipping it during ETR to USB disable. Adjust the
periodic flush threshold to the maximum value in order to
reduce the overhead when there is no data to be transferred.
CRs-Fixed: 461885
Change-Id: Ie3a1bbc80e017f187af56fcfdfb52297ba9aa72d
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Modify the CoreSight TMC driver for LPAE so that it can support
ETR physical addresses greater than 32 bits when LPAE is enabled.
Change-Id: I6db2c98c4db70262ab45f7ff11fe2a6846259f8a
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
Add support to reset each CoreSight cti device through sysfs. This
disables all cross triggering functionality on cti device by
unmapping all mapped cti trigins and cti trigouts and disabling the
cti device.
Change-Id: I4d1f48ad63e1317c893471e1818cd529dd2b002b
Signed-off-by: Aparna Das <adas@codeaurora.org>
The byte counter feature is enabled only if all the components it relies
on can be succesfully enabled.
Change-Id: I09e9b78c21af66d8cfc7c94d286f5b61adb7f7d6
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
For trace via sdc the sdc io regulator needs to be configured and enabled.
Add support for this in CoreSight driver instead of depending upon the
configured values of sdc io regulator on bootup.
Change-Id: I65f341c1dde58ee5e66372bcfb11393fc33bef54
Signed-off-by: Aparna Das <adas@codeaurora.org>
A check for the byte counter interrupt value being such that it
divides the memory reserved into equal size blocks is necessary
only when a non-zero value is specified.
Change-Id: I424c09322f2ee82917359d871f0916b3fb50b0be
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
Modify the hardware events driver so that it can handle the hardware event
mux control register addresses being greater than 32 bits.
Change-Id: Id41ce183fa946b14590947f21fbcea361393543f
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
Add support to show the CTI channels mapped onto CTI trigger inputs
and CTI trigger outputs via sysfs for each CTI block.
Change-Id: Ib105651f621516dc2055e72c371780cb4497e43a
Signed-off-by: Aparna Das <adas@codeaurora.org>
Do not allow mapping or unmapping the same cti trigin or cti trigout
multiple times onto the same ctm channel. Also prevent reference count
increment or decrement in this case which prevents incorrect enabling
or disabling of cti block.
Change-Id: Iebf7e2799e523f803f4509f5ab75fb238c7097ed
Signed-off-by: Aparna Das <adas@codeaurora.org>
The CoreSight block can produce an interrupt on transfer of
programmed number of bytes to ETR-memory. Use this feature
to provide an interface to manage the byte counter value and
to collect a continuous data stream from userspace.
Change-Id: Ic00c9b19483be566d0f05005936b4a6ff7ab52f1
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
Ensure correct value for number of bytes sent is returned by
stm_send function.
Change-Id: I866e9c1c95ab645ad54c5c4eb84a433421380cf5
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Add support to query CoreSight fuse state and fail the probe
if any of the required fuse(s) are disabled. This enables
a single image with CoreSight drivers compiled in to be run on
both Hardware that has CoreSight functionality disabled via fuse
or left enabled for use.
Change-Id: Ib770cc7f76e2b0644bda9600c92fc3a26823452d
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Add support for CoreSight Fuse driver which can be used by other
CoreSight drivers to query the state of the CoreSight fuses to
determine if the Hardware they manage is functionally disabled or
not.
Drivers can then take necessary actions like failing the probe if
the Hardware they manage is functionally disabled.
Change-Id: I2c2a2af064db750539b0ffa33870ddb7a2832e68
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Calling register_hotcpu_notifier inside of get/put_online_cpus
i.e. after taking the cpu_hotplug lock results in a deadlock
since register_hotcpu_notifier takes the cpu_add_remove_lock
which has already been acquired by the hotplug code before
requesting the cpu_hotplug lock.
Remove the get/put_online_cpus calls since they are not required.
CRs-Fixed: 501374
Change-Id: I3fb58265f6fedeb696d035d281af0d7904e28b79
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Flush ETR is mapped to TRIGIN[2] and so switch to using it in
order to cause a CTI trigger for TMC-ETR flush during wdog reset.
This avoids any race between TMC-ETR flush to memory and DDR
being put into self-refresh.
CRs-Fixed: 491986
Change-Id: Ia5e643121e040bd9c57c89a4b762b794bc8ddf62
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Move of_coresight.c from drivers/coresight to drivers/of where
all the of drivers files belong. of_coresight.c compilation will
now depend on CONFIG_CORESIGHT. Also make other appropriate
changes to Kconfig and Makefiles to support this.
This will allow other drivers using of_coresight.c apis to
compile and link successfully even when CONFIG_CORESIGHT is
disabled.
Change-Id: I05a32cb3f15767adf10de0a6b4b133e85a70e710
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Free temporarily allocated memory pointed to by seta_cfgs and
setb_cfgs when we are done using it.
Change-Id: Id3b27277fe1ed1897acb49ac8593d295108f0472
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Currently TPIU regualtor DT of node gets released on encountering
errors while reading voltage or current levels which can cause
use after free issues. Ensure the regulator of node gets released
only when we are completely done using it.
Change-Id: Ifaf8469aedb77e7d9fc6f71dab99417414f4e88d
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Add support for sdc regulators that don't have voltage or current
levels. This will allow tpiu output via sdc connector on chips
that power sdc connector with regulators without voltage and
current level support.
Change-Id: I03e9e94aebef3fc54a59922c50743ea8624bfdcf
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
The STM hardware event interface allows monitoring and tracing
of up to 32 hardware events. The CoreSight Hardware Event driver
programs various hardware event mux control registers to configure
these hardware events based on user selection. Currently APSS
controlled hardware event configurations are supported.
Change-Id: Ic2749ae1a8d405159cc7e8210dfc1d8864f96df9
Signed-off-by: Aparna Das <adas@codeaurora.org>
Switch to using EXPORT_SYMBOL from EXPORT_SYMBOL_GPL where
applicable to make export symbol api usage consistent for all
coresight drivers.
Change-Id: Iad00b6a55a23a9ae87a5534d523e4e1eb1c56395
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Vote for enabling clocks during hotplug ON in CPU_UP_PREPARE and
correspondingly vote to disable clocks in CPU_ONLINE or
CPU_UP_CANCELED callbacks until OS lock is unlocked. This is
required since memory mapped accesses to unlock the OS lock as
part of CPU_STARTING callback for some ARM based cpus need the
appropriate clocks to be on.
Change-Id: Ia9709692beb02654c225a0771c1eea556d581372
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Modify coresight drivers to perform resource lookup by name. The
coresight drivers now use the reg-names property specified in dt
nodes to lookup for resources.
Change-Id: I986f9687be81706d2424e288b9875c3a93e12d11
Signed-off-by: Aparna Das <adas@codeaurora.org>
Add support to allow tpiu to output trace data to the mictor or
sdc connectors depending upon user configuration via sysfs nodes.
This will allow tpiu trace usage without JTag hence improving the
usability.
Change-Id: I905f1ae844eb46faa9d0fceb47cd89c425110305
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
This change add the support for activating more than
one usb core in the system in bam to bam mode.
Potentially, we can have up to three usb cores in
the system: HSUSB, HSIC and DWC3.
This change simplify the USB BAM driver design, such that
we can easily define bam to bam paths for more than one usb
core concurrently with flexible peer BAMs configuration.
Change-Id: Ie5acb68f29e30cb6c14d2afd957ac8e21cc7beba
Signed-off-by: Shimrit Malichi <smalichi@codeaurora.org>
On CPUs which implement OS lock mechanism, the ETM driver needs to unlock
the OS lock in order to configure ETM registers. Implement OS unlock on
CPUs using a memory mapped access instead of cp14. This is necessary on
CPUs which implement OS lock mechanism and provide only memory mapped
accesss to ETM registers.
Change-Id: I1559cc32e77a5d3cd42badf4f81ca253cd316f5d
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
Add support for OST MIPI 1.0 protocol while using the simple
start token value of 0x10 for better performance since it avoids
sending the lenght field.
Use this standard OST MIPI 1.0 protocol except when only 64bit
writes are supported by STM in which case fallback to the
proprietary OST protocol.
CRs-Fixed: 433920
Change-Id: I73bcc44928a8807817b32636ca25b0aa82c7e4a9
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Krait v4 only supports cp15 CPMR_ETMCLKEN for turning on ETM
power/clock for subsequent cp14 accesses so use it instead of
ETMPDCR. Other Kraits also support cp15 CPMR_ETMCLKEN for turning
on ETM power/clock so it can be safely used for all Kraits.
Change-Id: I404b96d84a3c9329bf9a571db7ce57b91d9dc76c
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Add support for disabling TMC-ETR to USB BAM traffic (which can be
safely done in atomic context) as part of coresight_abort when
TMC-ETR-usb is the current sink.
Change-Id: I13f8989b3807cda89f81144a38be429ddaeb3d76
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Program TMC-ETR to stop on flush by default and dynamically
enable flush on watchdog reset using CTI when TMC-ETR-mem is
enabled and disable flush on watchdog reset when TMC-ETR-mem is
disabled.
This will help flush out pending data when a crash causes a
watchdog reset ensuring that most recent data gets captured in
the TMC-ETR-mem.
The need to dynamically enable and disable flush on watchdog
reset based on current sink state arises from ARM recommendation
to have CTI flush enabled only for one sink at a time.
CRs-Fixed: 455170
Change-Id: If780fe4709098b74860d4b32ab2d151e861cf10d
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Program TMC-ETF to stop on flush by default and dynamically
enable flush on watchdog reset using CTI when TMC-ETF (in circular
buffer mode) is enabled and disable flush on watchdog reset when
TMC-ETF (in circular buffer mode) is disabled.
This will help flush out pending data when a crash causes a
watchdog reset ensuring that most recent data gets captured in
the TMC-ETF.
The need to dynamically enable and disable flush on watchdog
reset based on current sink state arises from ARM recommendation
to have CTI flush enabled only for one sink at a time.
Change-Id: Ib1a57122802e335da776c008da20da68e8527b00
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Add support for CoreSight Cross Trigger Interface driver which
can be used to setup various cross-triggers available between
hardware blocks. This driver provides both an in kernel api as
well as a sysfs based user interface.
Change-Id: Idf445e6d1a3b082e0101b9b38926584527f1630f
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Rename control_trace.c to coresight-event.c to better align the
naming with the rest of coresight driver names.
Change-Id: I132a5df009339a041b21a4ef0cdd22d3c883d32e
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Change CONFIG_MSM_QDSS to granular CORESIGHT configs covering
various CoreSight drivers. This better represents the CoreSight
device topology and allows more flexibility in choosing the
drivers required for a particular platform or chip.
Change-Id: I5ae44442c24c88673f2045ad24dc89e4d86d23cb
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Move to using core_initcall instead of subsys_initcall for the
coresight core layer code so that drivers (eg. bus driver) that
probe early on can use the core layer coresight_register api in
their probe functions.
Change-Id: I8e7f208e177513d4da73d0931a4fa0767841b8cf
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Enhance error handling to provide graceful behavior in the case
of incorrect topology representation by the user. This
specifically improves the behavior when some of the required
device DT nodes are missed or required driver(s) are not
compiled.
Change-Id: I1bb72732a6f2d230775d8ce1ffec574adc3890d0
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Recommended ETR to usb flush procedure changed. This implements
the new recommended procedure.
CRs-Fixed: 443106
Change-Id: I18a6d457686905cbee75ce081ee4c6b4f6fdc62c
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Since USB recently started resetting USB BAM before calling the
cable connect callback, it is recommended that QDSS BAM is reset
before TMC ETR to USB connection is made in the TMC driver.
Change-Id: I37639b9ada69c9d5077812463c05ce5e6176a181
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
When ETM is enabled via kernel command line or config item but we
boot with maxcpus parameter value of less than number of present
cpus, cpus that are not included as part of maxcpus don't
get ETM enabled during kernel init since those cpus would not be
online.
This change ensures that for such cpus, first hotplug after the
respective cpu's ETM probe is done, enables ETM if it is enabled
via kernel command line or config item but hasn't already been
enabled.
Change-Id: Ie3613819896e781732b80d6be20f930b474418e8
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Enable and disable ETM during hotplug operations only if ETM is
allowed round-robin access by the funnel when all the ETMs share
the same funnel priority.
For 8960, 8064, etc it is observed that sometimes a core's ETM is
starved by other core ETMs constantly producing data. This works
around an issue seen where setting the prog bit of a core's ETMCR
(i.e. ETMCR[10]) doesn't result in that core's ETMSR[1] getting
set thereby triggering the "timeout while setting prog bit"
warning. Subsequently performaing a manual ETB flush as part of
disabling ETB to retrieve the collected trace data also fails.
Change-Id: I6dd37979058644495d945e80e6a2de4696fc5a20
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
smp_calls are cpu hotplug safe and so cpu hotplug locking isn't
required to safeguard them. Remove get_online_cpus() and
put_online_cpus() cpu hotplug locking calls that are currently
safeguarding smp_calls against cpu hoplugging.
Change-Id: I527403f4ffe088f3ee65b0b0899b398e1449ab48
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Reading block size to use for tmc-etr to usb transfers from DT
allows the flexibility to configure a different block size per
target.
Change-Id: I5b52db194ebb6fab7d3a02e8fb031bd9936fddd8
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Fail coresight_register if invalid (error or null) argument is
passed to avoid crashes.
Change-Id: I6c39ba2b81333f24480fdf5b348934651e095be5
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Remove using hardcoded value for the TMC ETR allocation size in
the TMC driver and instead get the size from the DT node. This
will ensure only one location (DT) controls the size of the
allocation.
Change-Id: I642d149e124c98470821ac4a37627747aecd2af7
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Dump TMC ETF and TMC ETR registers on abort to allow post crash
parsing. Also ensure magic value is written for TMC ETF buffer
dump.
Change-Id: I8f21c456bcc79ed3e2831bd6bd1e6a6dbfdb93d0
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
MSM9625 implements ETM based on ETM version 3.5.
As such the 9625 ETM registers need some additonal configuration
for ETM to be functional. They also have some extra registers which
need to be configured properly while some registers currently being
configured by the driver are absent on 9625. Additonally, the ETMv3.5
can be configured to support data tracing, support for which is
not present in the existing ETM driver.
Change-Id: Ic3e61d0d1abf371653a398a28111b308747a7b6f
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
When PC save is enabled via kernel command line or config item
but we boot with maxcpus parameter value of less than number of
present cpus, cpus that are not included as part of maxcpus don't
get PC save feature enabled during kernel init since those cpus
would not be online.
This change ensures that for such cpus, first hotplug after the
respective cpu's ETM probe is done, enables PC save feature if
the feature is enabled via kernel command line or config item but
hasn't already been enabled.
Change-Id: I9cae33654539ed72885fdf11cd603c7c776512c1
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Having both both ETMPDCR[3] set and ETMCR[0] cleared causes
pre-mature resumes from suspend power collapse. For now, clear
pwrup (ETMPDCR[3]) right after clearing pwrdwn (ETMCR[0]) to
avoid pre-mature resume from suspend power collapse.
Change-Id: I4b951ecc672d42aa9ea1feb7a5f999d24698405e
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Consistent with the what is done for TMC ETR, keep the
drvdata->size as representing the size of the actual buffer for
TMC ETF as well since size is used while dumping the buffer.
Change-Id: I2b5355a822898804add81c92bdd2992343195f2c
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Send data over STM only if the data length specified is non-zero.
This will avoid potential issues while avoiding sending empty
packets.
Change-Id: I1792d4b342bdb8cae2c0a8edc2d2584b42c72f6f
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Add support to transport data sent using userspace library over
STM. Data stream will contain the entity id, protocol id and
options.
Change-Id: I5bd1810338fd13373bbad7de559765002c43c500
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Fail ETM enable if the core is offline so that it is obvious to
the user that the operation failed. ETM disable cannot fail so
disable ETM during hotplugg off if it is user enabled and
re-enable ETM during hotplugg on if it is user enabled.
Change-Id: I24120582ff6d3c5f3598baff962dc2ef910c3a1e
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Switch to using spinlocks instead of mutexes to make apis
callable from atomic context.
Change-Id: I6c249b66c7f9db3d6028f1ab92bacfbcf43b150e
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Fail pcsave enable/disable if the core is offline so that it is
obvious to the user that the operation failed.
Change-Id: I2bd88636e1982a7de6b14f8b742d1f9bc7d23406
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Always clear ETMCR[pwrdwn] while enabling trace. This is used as
a logic enable and is a pre-requisite while enabling trace. So
switch to an implementation that does this and removes the save
and restore for pwrdwn and pwrup.
Change-Id: I8a14efe8fd76368ed1e177a701013a504aa1876f
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
For better throughput and to avoid limitations, use 2K block size
tranfers when outputting data over usb using ETR. Moreover, USB 3.0
currently only supports 2K block size for the descriptors.
Change-Id: Idc68c4d503e3ccca7715d3cbec21daedfbc2df6f
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Add runtime control for enabling/disabling program counter save feature.
Enabling program counter save feature will enable pc to be saved on
reset but implies ETM being left powered on. So we provide user runtime
control to enable the feature when debugging or disable it while taking
power measurements.
Change-Id: Ib007da851ee7f3b0fac195da62aac7def68cc67a
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Explicitly clear and set ETMCR power down bit as part of the ETM
register programming sequence since if this bit is set, writes to
some registers and fields might be ignored.
Moreover, ETMCR prog and power down bits are not directly modifiable
via the sysfs based MODE selction code. Instead they can implicitly get
modified by other code. So always preserve their values while
enabling ETM trace since the ctrl is a shadow of ETMCR bits that
are only modifiable via the sysfs based MODE selection code.
Change-Id: I842a42acdafb112759a1787ec6fc41140812020d
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Initialize buf for TMC ETR to the virtual address of the allocated
buffer memory. This will ensure a read on TMC ETR device node when ETF
is the current sink doesn't fail.
Change-Id: Id23dd9502ec728567c5b137354ca2d734f9309dc
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
coresight_abort allows for abruptly stopping the current sink from
accepting new data hence avoiding polluting trace with information
after the point of interest.
Depending upon the call site, coresight_abort could end up getting
called more than once. This change will help with ignoring
subsequent calls to coresight_abort so that abort callback is
called just once. This is in line with treating abort as a one time
abrupt stop.
Change-Id: I634001e832ee7fa1b23f67698bd2d5dd12f8d65d
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Use cp14 accesses to ETM registers for Krait v3 to avoid
limitations with memory mapped accesses.
Change-Id: Ia956eb0f5b45c748ffb5dd13dd14dc9595b9c68a
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Use ETMPDCR instead of ETMCR for ETM power/clock enable/disable. ETMPDCR
doesn't have corresponding cp14 access and hence will help with subsequent
multicore ETM support changes for 8974. ETMPDCR is available for PFTv1.1
and ETMv3.5 compliant ETM implementations.
Change-Id: I4b190b963cda29b406971cf075db36213b140495
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
A DLKM to abort tracing on an user space data, prefetch or
undefined instruction abort.
Change-Id: Iaba14628601ea6d3649e05423f8570131eea39f7
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
Move etm_arch_supported out of etm_init_arch_data to simplify the
init flow.
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Change-Id: I8a95f59e35e74c5af8c447abdc9f0dcd1682bce1
Add support to allow debug image to be able to dump ETF content
and ETM, TMC regsiters in case of apps proc bite or system hang
causing secure watchdog reset.
This will enable host parsing scripts to extract ETF and
ETR-memory trace data contents from RAM dumps.
Change-Id: Ie6f03bef7b4ccda7ea8d7709ee0c4808424c5b92
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Instead of writing FFCR bits 12 and 6 at once, sequence them i.e.
write bit 12 first to set ETB to stop on flush and followed by
setting bit 6 to trigger manual flush.
This should avoid any possible race between flush completing
before bit 12 getting set.
Change-Id: I0567701d34cb33a35d6bd876636a296532b9e400
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Change STM traceid from 3 to 16 so that ETM and STM can be used
concurrently if required. ATIDs 0 to 15 are reserved for ETM - one
for each core.
Change-Id: Ic51cf3b8baa9c22be69c952a20281b238750de5d
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Since we moved to separate enable nodes for each ETM, using pm_qos
to prevent power collapse of the target cpu while we enable or
disable ETM is less efficient and also susceptible to a race with
cpu hotplug.
Move to using smp call to enable and disable trace to avoid above
deficiencies with the newly re-structured code.
Change-Id: I65c726dbd6275af8db0d40db5034299287a02e91
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
With maxcpus=1, only core0 will be running with other cores in
reset until they are explicitly hotplugged on. To avoid reading
ETM registers for cores that are in reset during probe, use only
ETM0 for populating configuration info. For other ETM probes,
copy the info from ETM0.
Change-Id: I9ae4539b004956a026e919323413f9e3c7d5ba4a
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Memory reservation is now required for carve outs. Add appropriate
memory reservation driver support for the TMC ETR carve out.
Change-Id: I31cda1317d31555b70a034eae4c6fdadacd36fdb
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Ensure that buffer pointer points to the right location while
trying to read TMC in ETR circular buffer mode when we wrap
around.
TMC in ETR circular buffer mode tracks the physical address
in the RWP register (in contrast to pure offsets). Hence
subtract it from the base physical address to get the offset.
Change-Id: Ice1170dcd63928dd8304c421800848e036386b88
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Program STM to allow TRIGOUTHETE output (that feeds into the CTI input)
to be asserted when hardware events occur. Also program the STM sync
frequency to 1023 byte interval.
Change-Id: Ia4c9c73d61a50dfc5eb2df5f52921831b647df0e
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Support for etr to usb trace output using QDSS BAM to USB BAM
transfers.
Change-Id: Ibb6f8d0cf1d9799668cb22ccaa13966139c8dea5
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Bottom 8 bits [7:0] of ETMSYNCFR are reserved on Krait pass3. This
means only bits [11:8] are valid since bits [31:12] are specified
as reserved by PFTv1.1 specification.
Use an appropriate value for the synchronization frequency in light
of this change on Krait pass3.
Change-Id: I5f32ad6546fc8a72e0a222cc90e0f23c9779ee3c
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Have STM hardware event and port enable sysfs nodes to allow users to
selectively enable and disable either hardware events or stimulus
ports while STM as a whole is enabled.
Change-Id: I32c23f62a3782487e67eb5e6a9da5a5bf7e11df8
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Provide CoreSight abort debug api to stop the active trace sink
from any context. This is a best effort api that can be used to
abruptly stop and disable the current trace sink from anywhere
in the kernel to avoid tracing and hence polluting the trace data
after the point of interest has been executed.
Change-Id: I34c528d9febec4265088a7267dbcf0e7a1f87fcf
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
This driver manages CoreSight TMC (Trace Memory Controller) which
can be pre-configured as an ETF (Embedded Trace FIFO) or ETR
(Embedded Trace Router). ETF when configured in circular buffer mode
acts as an ETB (Embedded Trace Buffer).
Change-Id: I1ca40e1fbd3049dc7addb834c064ab3a6c4c22e0
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Support for reading hardware data for CoreSight devices from device
tree.
Change-Id: I4d149991c89b458384465d163386084f500a4028
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Using devm_* apis helps in simplifying driver init and exit paths,
hence switch to using them in the driver probe calls.
Change-Id: I41aba1129f6638fcee859e57f957fa3f14c1c439
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
This driver manages the CoreSight Replicator that has been made
programmable to allow software to turn of the replicator branch
to sink that is not being used. This avoids trace traffic to the
unused/non-current sink from causing backpressure that results in
overflows at the source.
Change-Id: Idf82149d5dc3702b6da59147e4d9d5e532032161
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Switch all CoreSight drivers to start using the new CoreSight core
layer code. Remove obsolete qdss code.
Change-Id: I2d4496aea0ffd918e0bfbf4b4e58ad82ea634a59
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Some targets require tpiu is disabled before other sinks like ETB
get enabled to get proper ETM trace.
Change-Id: Idcacf7b6515fd17c3a49c74a338258f02631f7cc
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
This allows users to switch between available trace sinks thus
providing user to choose the best switch for the debug use case.
Change-Id: I0c90396010cfcd9f3ab9d3c6d4c1cc7230632c42
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Complete the rename by changing cs to coresight for variables,
functions and constants.
Change-Id: I506d5872e5c09f201c4f3674d7722d36eca26921
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Since cs is not a well known acronym for CoreSight, rename
directory and files from cs to coresight.
Change-Id: I5f9b12794b80b1c01c9ce0621d53ee6be408a361
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
Sarangdhar Joshi
Linux Build Service Account
Pratik Patel
Aparna Das
Sujeet Kumar
Xiaogang Cui
Dipen Parmar
Xiaocheng Li
Ian Maund
Pushkar Joshi
Shimrit Malichi