Commit Graph

242 Commits

Author SHA1 Message Date
Saranya Chidura f32fe96ca8 coresight: tmc: Fix use after free issue with tmc read
Fix race condition seen between reading tmc buffer and enabling
the device. The race condition can result in a use after free
issue if the buffer is released while a read is in progress.

Signed-off-by: Saranya Chidura <schidura@codeaurora.org>
Change-Id: I9908fa78acbf3152ee791c63fef525f09a9a23d5
2017-07-30 10:34:00 -07:00
Charan Teja Reddy 2c23067f45 coresight: fix the dangling pointer issues on coresight
Fix the dangling pointer issues on CoreSight that can cause kernel
panic.

Change-Id: If3abe89bf0326230c29a49d293ab22ebcec93076
Signed-off-by: Charan Teja Reddy <charante@codeaurora.org>
2016-09-14 05:02:11 -07:00
Charan Teja Reddy 9ed4b8f4b2 coresight: fix use-after-free in stm on secure boot devices
When the STM driver failed to register, the stmdrvdata variable becomes
dangling pointer which may cause APSS to crash.

Change-Id: I0e709ac180d8c946f25e026b23edadb08c82a1f3
Signed-off-by: Charan Teja Reddy <charante@codeaurora.org>
Signed-off-by: Swetha Chikkaboraiah <schikk@codeaurora.org>
2016-08-01 22:09:15 -07:00
Sarangdhar Joshi d2f8e5d2f9 coresight: register to cpu_pm notifiers for cti save / restore
coresight_cti_ctx_save() and coresight_cti_ctx_restore() are
called directly from lpm-levels driver. These functions will no
longer be called from lpm-levels driver when we move to PSCI
framework.  Add support in coresight-cti driver to rely on cpu_pm
callback for save and restore functionality of CPU CTI configuration.

Change-Id: I715dcc2297709b7d903d9bd7752a68864477fd6c
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
Signed-off-by: Charan Teja Reddy <charante@codeaurora.org>
2015-10-26 23:57:06 -07:00
Sarangdhar Joshi 25e2db24e3 soc: qcom: jtagv8: register for hotplug and cpu_pm notifiers
msm_jtag_save_state() and msm_jtag_restore_state() are called
directly from msm-pm driver. However msm-pm driver is going to be
deprecated when we move to PSCI framework. Add support in jtagv8
driver to rely on hotplug and cpu_pm callbacks for save and
restore functionality of Debug and ETM registers.

This commit also modifies the hotcpu callback in ETM driver to
avoid any race condition with hotcpu callback from Jtagv8 driver
that has been introduced in this commit.

Change-Id: I1261fdcb548b7a21b37090426efdbd77ea038333
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
Signed-off-by: Xiaogang Cui <xiaogang@codeaurora.org>
2015-08-12 21:50:10 -07:00
Xiaogang Cui 3417561b1f coresight: add support to force dump tmc registers during tmc_enable
Add boolean property to force dump TMC registers during tmc_enable().
This is required for cases where TMC registers are not retained across
watchdog reset workflows.

Change-Id: I08c54f8b0b747436dec488e9421e08684f602c26
Signed-off-by: Xiaogang Cui <xiaogang@codeaurora.org>
2015-07-16 03:53:25 -07:00
Sarangdhar Joshi 6c9fa7bf52 coresight: enable timestamp request based on trigger input
Set the variable to enable timestamp request based on trigger
input by default for CMB dataset type.

Change-Id: I38e641874a287961d5a8cd72bb13737ff4bcc974
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
2015-07-03 09:08:18 -07:00
Sarangdhar Joshi f2266e0132 coresight: add cmd dataset validation checks
Add validation checks for CMB dataset type to avoid users
accessing CMB device attributes when CMB dataset type is not
supported.

Change-Id: I25fbf18a8895d4b2db84c92ee871af858fdd05bb
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
2015-06-20 08:46:27 -07:00
Sarangdhar Joshi 165f99d455 coresight: modify code for cmd dataset type
Modify TPDM driver code for CMD dataset type. This is in
prepration to support additional dataset types in TPDM driver.

Change-Id: Ia8f5a662c161900fc0a5a0fd3e0c0385202229b9
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
2015-06-20 08:46:03 -07:00
Xiaogang Cui 118d936456 coresight: make boot_enable support individual remote etm enablement
Currently boot_enable supports enabling all remote ETM devices or none.
Make it granular to support individual remote ETM device enablement
thereby providing more control and flexibility.

Change-Id: Ie8526591f617456fcfa03178a24510a9cbd73cba
Signed-off-by: Xiaogang Cui <xiaogang@codeaurora.org>
2015-05-14 14:45:43 +08:00
Linux Build Service Account 401b12a383 Merge "coresight: restrict the available out modes to the ones from device tree" 2015-05-10 08:48:18 -07:00
Pratik Patel 5564253183 coresight: disable spmi handshake while enabling qpdi
SPMI handshake configuration was added on newer chips but isn't
quite supported. Ensure it remains disabled while enabling or
disabling qpdi feature to avoid side effects on qpdi
functionality.

Change-Id: I222ec1c42b483208ac640a9039b6eb042a6bae79
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
2015-05-06 15:12:43 -07:00
Shaoqing Liu 6493f0d2da coresight: unify remote processor etm drivers
Unify modem, wcn, rpm, audio processor ETM drivers into a single remote
processor ETM driver.

Change-Id: I143b19f3a7be65bb476f57da924be2572a7add6a
Signed-off-by: Shaoqing Liu <shaoqingliu@codeaurora.org>
Signed-off-by: Xiaogang Cui <xiaogang@codeaurora.org>
2015-04-30 01:18:17 -07:00
Sarangdhar Joshi f8c4d52748 coresight: add tpda enable validation checks in sysfs show functions
TPDA clocks are voted during TPDA enable and un-voted during TPDA
disable. Read TPDA registers only when TPDA is enabled to avoid
any unclocked access. Add TPDA enable validation checks before
reading TPDA flush registers via sysfs show functions. These validation
checks are already present in sysfs store functions used for making TPDA
flush request.

CRs-Fixed: 819721
Change-Id: Icbb530d9a1c1aad516f137c3faaf4c7d0373265c
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
2015-04-08 12:57:16 -07:00
Xiaogang Cui dc1f7f3d5a coresight: restrict the available out modes to the ones from device tree
Add check in coresight TPIU driver to show the avilable out_modes
from device tree entries.

Change-Id: Ica4c75687e57de380b4de5029b768a9d3a651ee9
Signed-off-by: Xiaogang Cui <xiaogang@codeaurora.org>
2015-04-03 11:21:06 +08:00
Sarangdhar Joshi 42f54e4d7f coresight: type cast 32-bit physical address to phys_addr_t
TMC_ETR_SG_ENT_TO_BLK macro performs bit manipulations on the entry in
scatter gather table for TMC-ETR DDR configuration to convert it to
physical address pointing to 4K blocks of physical memory.

On 64-bit architecture, the top 32-bits are lost if 32-bit address is
passed to this macro and value becomes 64-bit after bit manipulation. Type
cast 32-bit physical address to phys_addr_t when passing to
TMC_ETR_SG_ENT_TO_BLK macro.

Change-Id: I37b1c4aaeed6bcd1a9fbeaea4821881e6e1d9e39
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
2015-03-14 04:23:56 -07:00
Xiaogang Cui 8eee547337 coresight: add debugui driver support
DebugUI can capture data on certain triggers. It can also send the
captured data as trace output. Add driver support for this to help with
debugging issues.

Change-Id: Ia57240c915b90747453198fa3d7ae41ab9f658fb
Signed-off-by: Xiaogang Cui <xiaogang@codeaurora.org>
2015-03-03 09:56:19 +08:00
Sarangdhar Joshi 992db96510 coresight: correctly set bits for bc, tc and dsb element size
BC, TC and DSB element size needs to be programmed in one of the TPDA
register.  Correctly set bits representing BC, TC and DSB element size.

Change-Id: I1ea1936539c5c4a117b86bc6193b7acf4872e62c
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
2015-02-28 16:49:56 -08:00
Sarangdhar Joshi bc55a64b3a coresight: use dt property to specify atid for tpda
Add support to use device tree property to specify ATID value required
for supporting multiple TPDAs.

Change-Id: Id032a7cb3ceab35763f81155d1b8c50bb513be7b
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
2015-02-09 15:38:38 -08:00
Sarangdhar Joshi 4a053c13ab coresight: add element size support for dataset types
Add support for setting up the element size value per TPDA port for various
dataset types as this is necessary for TPDA functionality.

Change-Id: I36e7d849634d1576b5591337479cc92b77b3f395
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
2015-02-05 08:27:11 -08:00
Sarangdhar Joshi 981437e636 coresight: add device attributes to support flush request
TPDA supports global and per port flush request options. Add device
attributes in TPDA driver to honor these options.

Change-Id: I5d6cbde775375b78fd0aae0734244b3753dee426
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
2015-02-04 14:48:28 -08:00
Sarangdhar Joshi 29bf969f2a coresight: set only required bits in the bitmap
Register value passed to the bitmap_fill was incorrectly setting
unnecessary extra bits in bitmap. Set only required bits in the bitmap.

Change-Id: I00630d1fd0c4ef759f45cd13efa121baa3e4df11
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
2015-01-31 16:19:07 -08:00
Sarangdhar Joshi cd587cb95a coresight: vote for core clock before accessing tpdm register
TPDM register accesses need core clock to be ON. Vote for core clock
before accessing TPDM register.

Change-Id: I329f45d00eee486a9aa4eb005aed1ac9bec3ea56
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
2015-01-28 15:28:40 -08:00
Sarangdhar Joshi f21ac4d352 coresight: add support for new fuse layout on thulium
CoreSight fuse layout has changed for thulium. Add support in driver to
honor the new fuse layout.

Change-Id: I2b5b0e7a417ec01067942689f6e22e54ec56782d
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
2015-01-21 13:30:07 -08:00
Linux Build Service Account fd2e03a244 Merge "coresight: use instance id from device tree" 2014-12-16 01:42:45 -08:00
Xiaogang Cui 0208cdf631 coresight: set etmdrvdata just before put_online_cpus
Due to race conditions, ETM initialization can fail if cpu hotplug
occurs while ETM probe is ongoing. Move etmdrvdata initialization
just before put_online_cpus() to prevent this race condition.

Change-Id: Iac943e5498d30554f5cb8bca4a9fe8e32bdf4030
Signed-off-by: Xiaogang Cui <xiaogang@codeaurora.org>
2014-12-12 10:21:02 +08:00
Xiaogang Cui 51864eb3eb coresight: use instance id from device tree
Move instance id to device tree to support multiple remote ETM
devices with different instance ids.

Change-Id: Ief6487df417403727dd78bb404aee5fceac54ced
Signed-off-by: Xiaogang Cui <xiaogang@codeaurora.org>
2014-12-08 11:16:33 +08:00
Pratik Patel d80f463610 coresight: add header meta data for every ost packet sent via stm
Add header meta data carrying useful info like version, magic,
task name, cpu and kernel timestamp with every OST packet sent
using STM.

This will help provide additional info that can be used for STM
log analysis.

Change-Id: I8902f5529d62417ee8b4d6a21f3801c06edce972
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
2014-11-18 19:08:30 -08:00
Pratik Patel 52c3a5df57 coresight: add dsb sy barrier to stm data writes
Add dsb sy barrier to stm data writes to avoid getting into a
situation where many writes are outstanding due to stm logging.
This helps avoid a cpu errata condition that gets triggerred with
heavy stm logging.

Change-Id: I7664fa3ccfcd8ac05514eb5e4db9441db9d809a2
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
2014-11-05 11:12:20 -08:00
Sarangdhar Joshi 4608aacb30 coresight: modify frequency request device attribute name
Modify device attribute name for frequency request to make it more
intuitive.

Change-Id: I4fe3f8eeb1ab1abe0eae3bcb684cdc6c2bb6b034
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
2014-10-31 15:01:55 -07:00
Sarangdhar Joshi 448bc9753a coresight: set the flag to request timestamp for freq packets
Set the flag to request timestamp by default for frequency packets. User
can clear the flag if timestamp is not required for frequency packets.

Change-Id: Iabddf7eaedeef2cd1d264a7db9c99f6bdf43bfd9
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
2014-10-31 13:54:14 -07:00
Xiaogang Cui 1daf7a8fef coresight: add attributes to show available modes and mem-type options
Add available_out_modes and available_mem_types device attributes to
provide information on available out modes and memory type options
supported for TPIU and TMC configurations.

Change-Id: Iec02c42877aa75f024590bf112d1c33eb4ad5e46
Signed-off-by: Xiaogang Cui <xiaogang@codeaurora.org>
2014-10-21 13:53:36 -07:00
Pratik Patel 78ea56557a coresight: use correct mutex lock for cti show functions
Use the correct mutex lock for CTI show functions to ensure
proper mutual exclusion while referencing refcnt.

Change-Id: I8c5b69526bbd46630f5f9d5a3c4b4542b065da11
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
2014-10-13 21:43:12 -07:00
Pratik Patel 7490eb5e7f coresight: don't call clk apis from atomic context
Rearrange CTI clock voting to avoid calling clk_prepare_enable
and clk_disable_unprepare apis from atomic context. This will
prevent scheduling while in atomic context.

Change-Id: I0b8a484cb38d67255dc6f0ba7c6162252d1f0c8e
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
2014-10-13 21:43:11 -07:00
Linux Build Service Account cfb19d6189 Merge "coresight: remove an unnecessary if statement which validates cpu id" 2014-10-12 05:41:08 -07:00
Sarangdhar Joshi d5d3b94090 coresight: remove an unnecessary if statement which validates cpu id
CPU id returned by raw_smp_processor_id() is guaranteed to be less than
NR_CPUS. So etmdrvdata array will never do out of bound accesses. Remove an
unnecessary if statement which validates this.

Change-Id: I4a46f488ba8583cfbc5bc44c7679fb93a6f6b09b
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
2014-10-09 16:08:17 -07:00
Pratik Patel 1bbccd2f87 coresight: add support for cti save disable
Add support to disable CTI save and restore to avoid voting for
CTI clock during probe as well as the associated save and restore
latency at the cost of breaking cpu CTI support on targets where
cpu CTIs have to be preserved across power collapse.

This allows for low overhead CTI support where cpu CTI usage is
not required but the target requires cpu CTIs to be preserved
across power collapse.

Change-Id: I0545d3442d1d6b2f707da7f56d029a7df2f7cae9
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
2014-10-01 12:57:47 -07:00
Pratik Patel 2a9c456e8b coresight: check cpu node for cpu ctis independent of cti save
Validate cpu node for cpu CTIs independent of cti save being set
for the respective cpu CTI. This allows for failing the probe if
the cpu node for cpu CTI does not match with one of the cpus in
the cpu possible mask irrespective of whether the target requires
cpu CTI save and restore across power collapse.

Change-Id: I1ebabedf9b14c15f376e06389c22cb71caf851af
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
2014-10-01 12:57:46 -07:00
Pratik Patel 08c003ea55 coresight: remove cti-ack-atomic support
Remove cti-ack-atomic dt property usage since CTI clock is now
guaranteed to be enabled as long as a mapping exist on the CTI.

This removes the need to explicitly vote for CTI clock based on
the property during probe and it is neither required to skip the
clock enablement in coresight_cti_ack_trig() since CTI clock
enablement in coresight_cti_ack_trig() is not need and is
removed.

Change-Id: I74335b6f124f4cbaadcc58fca10cf3e54f2f39fb
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
2014-10-01 12:57:46 -07:00
Pratik Patel cf06ad136c coresight: revert to map/unmap based clock usage for cti driver
This reverts commit 8b4b8afff7 with
merge conflict resolutions.

CTI clock is required to be on for the CTI to pass the cross
trigger events and hence the revert to voting for clocks as part
of the first map on a CTI and unvoting the clocks as part of the
last unmap on a CTI.

Change-Id: I98901443c6526e223853403e2ff1a0eea2adbf83
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
2014-10-01 12:57:45 -07:00
Pratik Patel 0cd7ef13fc defconfig: explicitly enable coresight cti on msm targets
Remove implicit selection of CoreSight CTI driver from Kconfig
and instead explicitly enable it in various msm defconfigs. This
gives the flexibility to selectively enable or disable CTI driver
on a defconfig for a particular target.

Change-Id: I328aa53cdcaade0bbb6bf1b0d7f4f221a5e31518
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
2014-10-01 12:57:45 -07:00
Xiaogang Cui 9ac709e17d coresight: enable SD only mode when hardware sensing is not enabled
cd_gpio is floating on some devices, then there is a possiblity
that a false CARD_DETECT toggle is created when software starts to
resume SD card from power collapse at the same time. SD driver resume
will fail due to collision.

Change-Id: I5b33da09fe8d71ea2fa381f98f1dd79286d28399
Signed-off-by: Xiaogang Cui <xiaogang@codeaurora.org>
2014-09-29 10:37:29 +08:00
Linux Build Service Account 0136d91d63 Merge "coresight: add tpda and tpdm driver support" 2014-09-23 19:47:51 -07:00
Sarangdhar Joshi c3d8863ae0 coresight: add tpda and tpdm driver support
Add TPDA and TPDM driver support required for trace, profiling & diagnostic
data collection and retrieval. Monitors are responsible for data set
collection and aggregators are useful for pulling the datasets from one or
more attached monitors and pushing the resultant data out.

Change-Id: I15097a62ca1c100f38409abc4bf92793e8187d70
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
2014-09-20 13:28:28 -07:00
Pratik Patel 9609f534ff coresight: use pr_err_ratelimited for coresight abort error
Switch to using pr_err_ratelimited so as to not flood the logs if
coresight_abort gets called repeatedly from panic while the
semaphore is acquired but not released.

Change-Id: Ife180795be0e605c587b117eb0441081b154da5e
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
2014-09-19 16:56:54 -07:00
Xiaogang Cui 567cd1b6bb coresight: add checks to avoid crash for coresight fuse
Add more checks for coresight fuse driver to avoid device crash
when coresight fuse driver is enabled but dt node is missing.

Change-Id: Ib18feec45ec81ae4aa64b94e1691364fea56a826
Signed-off-by: Xiaogang Cui <xiaogang@codeaurora.org>
2014-08-21 13:11:30 +08:00
Neeti Desai ddb78a2941 coresight: add checks to validate etm trace unit resource values
Hardware sets the register values to indicate how many resources the trace
unit supports. Add checks to validate these values to avoid any out of
bounds access.

Change-Id: I5f19a1351af3bc727f6fb7743a258727fa80fc06
Signed-off-by: Neeti Desai <neetid@codeaurora.org>
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
2014-08-08 19:00:55 -07:00
Sarangdhar Joshi 719767d522 coresight: add spinlock across stm channel allocation
There appears to be a race condition during stm channel allocation where
two processes running in parallel get same channel. Fix this by adding a
spinlock across channel allocation logic until we figure out a root cause
of this issue.

Change-Id: Ifcc655957adae3c58d8b329d8cd5c0551a26d5c6
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
2014-08-01 10:37:12 -07:00
Linux Build Service Account b2d1039d14 Merge "coresight: get etm funnel port for associated cpu" 2014-07-29 09:53:17 -07:00
Linux Build Service Account 64c9c7d17b Merge "coresight: make etm probe independent of core0" 2014-07-29 09:53:16 -07:00