Reduce the pinctrl overhead in the msm spi driver code.
Change-Id: I19854ecdcd4230bfda946c773bc39909508c0891
Signed-off-by: Dan Sneddon <dsneddon@codeaurora.org>
ice40 bridge chip driver uses delay_usecs option, due to which this message
floods the dmesg logs. So change it's logging level to dev_dbg.
CRs-Fixed: 655184
Change-Id: I3b7016237322763002209b9fc021f0af0f7af687
Signed-off-by: Tarun Gupta <tarung@codeaurora.org>
When transfer speed exceeds the maximum supported frequency,
cur_msg is not initialized, Thus accessing the same cause kernel
crash. This patch corrects this.
CRs-Fixed: 647032
Change-Id: Ic0487a6b8859040f57c085fdcd78093480e64d49
Signed-off-by: Sana Venkat Raju <c_vsana@codeaurora.org>
Spi doesn't handle multiple xfer per message scenario
(eg:Rd->Wr or Wr->Rd) correctly and spi request
stuck indefinetly in while loop when total byte count
is not 0.
increment both(rx,tx) references so next bam
transaction will be queued correctly. Flush the
bam pipes after each transactions.
CRs-Fixed: 637693
Change-Id: I455df38be2f9687b1eb2a704466f6974dfb83a22
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
The following commits have been reverted from this merge, as they are
known to introduce new bugs and are currently incompatible with our
audio implementation. Investigation of these commits is ongoing, and
they are expected to be brought in at a later time:
86e6de7 ALSA: compress: fix drain calls blocking other compress functions (v6)
16442d4 ALSA: compress: fix drain calls blocking other compress functions
This merge commit also includes a change in block, necessary for
compilation. Upstream has modified elevator_init_fn to prevent race
conditions, requring updates to row_init_queue and test_init_queue.
* commit 'v3.10.28': (1964 commits)
Linux 3.10.28
ARM: 7938/1: OMAP4/highbank: Flush L2 cache before disabling
drm/i915: Don't grab crtc mutexes in intel_modeset_gem_init()
serial: amba-pl011: use port lock to guard control register access
mm: Make {,set}page_address() static inline if WANT_PAGE_VIRTUAL
md/raid5: Fix possible confusion when multiple write errors occur.
md/raid10: fix two bugs in handling of known-bad-blocks.
md/raid10: fix bug when raid10 recovery fails to recover a block.
md: fix problem when adding device to read-only array with bitmap.
drm/i915: fix DDI PLLs HW state readout code
nilfs2: fix segctor bug that causes file system corruption
thp: fix copy_page_rep GPF by testing is_huge_zero_pmd once only
ftrace/x86: Load ftrace_ops in parameter not the variable holding it
SELinux: Fix possible NULL pointer dereference in selinux_inode_permission()
writeback: Fix data corruption on NFS
hwmon: (coretemp) Fix truncated name of alarm attributes
vfs: In d_path don't call d_dname on a mount point
staging: comedi: adl_pci9111: fix incorrect irq passed to request_irq()
staging: comedi: addi_apci_1032: fix subdevice type/flags bug
mm/memory-failure.c: recheck PageHuge() after hugetlb page migrate successfully
GFS2: Increase i_writecount during gfs2_setattr_chown
perf/x86/amd/ibs: Fix waking up from S3 for AMD family 10h
perf scripting perl: Fix build error on Fedora 12
ARM: 7815/1: kexec: offline non panic CPUs on Kdump panic
Linux 3.10.27
sched: Guarantee new group-entities always have weight
sched: Fix hrtimer_cancel()/rq->lock deadlock
sched: Fix cfs_bandwidth misuse of hrtimer_expires_remaining
sched: Fix race on toggling cfs_bandwidth_used
x86, fpu, amd: Clear exceptions in AMD FXSAVE workaround
netfilter: nf_nat: fix access to uninitialized buffer in IRC NAT helper
SCSI: sd: Reduce buffer size for vpd request
intel_pstate: Add X86_FEATURE_APERFMPERF to cpu match parameters.
mac80211: move "bufferable MMPDU" check to fix AP mode scan
ACPI / Battery: Add a _BIX quirk for NEC LZ750/LS
ACPI / TPM: fix memory leak when walking ACPI namespace
mfd: rtsx_pcr: Disable interrupts before cancelling delayed works
clk: exynos5250: fix sysmmu_mfc{l,r} gate clocks
clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg clock
clk: samsung: exynos4: Correct SRC_MFC register
clk: clk-divider: fix divisor > 255 bug
ahci: add PCI ID for Marvell 88SE9170 SATA controller
parisc: Ensure full cache coherency for kmap/kunmap
drm/nouveau/bios: make jump conditional
ARM: shmobile: mackerel: Fix coherent DMA mask
ARM: shmobile: armadillo: Fix coherent DMA mask
ARM: shmobile: kzm9g: Fix coherent DMA mask
ARM: dts: exynos5250: Fix MDMA0 clock number
ARM: fix "bad mode in ... handler" message for undefined instructions
ARM: fix footbridge clockevent device
net: Loosen constraints for recalculating checksum in skb_segment()
bridge: use spin_lock_bh() in br_multicast_set_hash_max
netpoll: Fix missing TXQ unlock and and OOPS.
net: llc: fix use after free in llc_ui_recvmsg
virtio-net: fix refill races during restore
virtio_net: don't leak memory or block when too many frags
virtio-net: make all RX paths handle errors consistently
virtio_net: fix error handling for mergeable buffers
vlan: Fix header ops passthru when doing TX VLAN offload.
net: rose: restore old recvmsg behavior
rds: prevent dereference of a NULL device
ipv6: always set the new created dst's from in ip6_rt_copy
net: fec: fix potential use after free
hamradio/yam: fix info leak in ioctl
drivers/net/hamradio: Integer overflow in hdlcdrv_ioctl()
net: inet_diag: zero out uninitialized idiag_{src,dst} fields
ip_gre: fix msg_name parsing for recvfrom/recvmsg
net: unix: allow bind to fail on mutex lock
ipv6: fix illegal mac_header comparison on 32bit
netvsc: don't flush peers notifying work during setting mtu
tg3: Initialize REG_BASE_ADDR at PCI config offset 120 to 0
net: unix: allow set_peek_off to fail
net: drop_monitor: fix the value of maxattr
ipv6: don't count addrconf generated routes against gc limit
packet: fix send path when running with proto == 0
virtio: delete napi structures from netdev before releasing memory
macvtap: signal truncated packets
tun: update file current position
macvtap: update file current position
macvtap: Do not double-count received packets
rds: prevent BUG_ON triggered on congestion update to loopback
net: do not pretend FRAGLIST support
IPv6: Fixed support for blackhole and prohibit routes
HID: Revert "Revert "HID: Fix logitech-dj: missing Unifying device issue""
gpio-rcar: R-Car GPIO IRQ share interrupt
clocksource: em_sti: Set cpu_possible_mask to fix SMP broadcast
irqchip: renesas-irqc: Fix irqc_probe error handling
Linux 3.10.26
sh: add EXPORT_SYMBOL(min_low_pfn) and EXPORT_SYMBOL(max_low_pfn) to sh_ksyms_32.c
ext4: fix bigalloc regression
arm64: Use Normal NonCacheable memory for writecombine
arm64: Do not flush the D-cache for anonymous pages
arm64: Avoid cache flushing in flush_dcache_page()
ARM: KVM: arch_timers: zero CNTVOFF upon return to host
ARM: hyp: initialize CNTVOFF to zero
clocksource: arch_timer: use virtual counters
arm64: Remove unused cpu_name ascii in arch/arm64/mm/proc.S
arm64: dts: Reserve the memory used for secondary CPU release address
arm64: check for number of arguments in syscall_get/set_arguments()
arm64: fix possible invalid FPSIMD initialization state
...
Change-Id: Ia0e5d71b536ab49ec3a1179d59238c05bdd03106
Signed-off-by: Ian Maund <imaund@codeaurora.org>
commit 61d1cf163c8653934cc8cd5d0b2a562d0990c265 upstream.
The 'ath79_spi_setup_cs' function initializes the chip
select line of a given SPI device in order to make sure
that the device is inactive.
If the SPI_CS_HIGH bit is set for a given device, it
means that the CS line of that device is active HIGH
so it must be set to LOW initially. In case of GPIO
CS lines, the 'ath79_spi_setup_cs' function does the
opposite of that due to the wrong GPIO flags.
Fix the code to use the correct GPIO flags.
Reported-by: Ronald Wahl <ronald.wahl@raritan.com>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: Mark Brown <broonie@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
As part of pinctrl frame work migration, add support
for chip select GPIO configuration using pinctrl frame work.
Now SPI driver supports both pinctrl frame work as
well as GPIO mux to configure chip select GPIO's.
CRs-Fixed: 621109
Change-Id: Id4aa58f9e2d2ae667719c6c600fb35b88b0f5b77
Signed-off-by: Sana Venkat Raju <c_vsana@codeaurora.org>
Chip select GPIO can be free during the suspend.
Duplicate chip select free causing RX SPI data
Corruption recently reported from customers, this
Patch corrects this.
CRs-Fixed: 626641
Change-Id: Ib80516b6d43c7185586a8815c4430446a9e31ce0
Signed-off-by: Sana Venkat Raju <c_vsana@codeaurora.org>
Bam parameter variable types for physical address
and handles are defined incorrectly for 64 bit bam.
Correct the variable types.
CRs-Fixed: 622639
Change-Id: Ia886406dd4a43b6f2eaa584a7deb717da5618e81
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
commit 1f802f8249a0da536877842c43c7204064c4de8b upstream.
This reverts commit e120cc0dcf2880a4c5c0a6cb27b655600a1cfa1d.
It causes a NULL pointer dereference with drivers using the generic
spi_transfer_one_message(), which always calls
spi_finalize_current_message(), which zeroes master->cur_msg.
Drivers implementing transfer_one_message() theirselves must always call
spi_finalize_current_message(), even if the transfer failed:
* @transfer_one_message: the subsystem calls the driver to transfer a single
* message while queuing transfers that arrive in the meantime. When the
* driver is finished with this message, it must call
* spi_finalize_current_message() so the subsystem can issue the next
* transfer
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Signed-off-by: Mark Brown <broonie@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
During multiple transfers, currently SPI
driver imposes check for read/write length,
If read/write length is greater than FIFO size
the transaction are failing due to this check.
This patch removes this check to successfully
transfer the data during multiple transfers of
size greater than FIFO size.
CRs-Fixed: 592431
Change-Id: I5e24744155d585811a280a213f8d7f298027cd5b
Signed-off-by: Sana Venkat Raju <c_vsana@codeaurora.org>
commit e120cc0dcf2880a4c5c0a6cb27b655600a1cfa1d upstream.
This corrects a problem in spi_pump_messages() that leads to an spi
message hanging forever when a call to transfer_one_message() fails.
This failure occurs in my MCP2210 driver when the cs_change bit is set
on the last transfer in a message, an operation which the hardware does
not support.
Rationale
Since the transfer_one_message() returns an int, we must presume that it
may fail. If transfer_one_message() should never fail, it should return
void. Thus, calls to transfer_one_message() should properly manage a
failure.
Fixes: ffbbdd2132 (spi: create a message queueing infrastructure)
Signed-off-by: Daniel Santos <daniel.santos@pobox.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit 86b3bde003e6bf60ccb9c09b4115b8a2f533974c upstream.
The spi command must include the full message length including any
prepended writes, else transfers larger than 256 bytes will be
incomplete.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
Acked-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Mark Brown <broonie@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
After the last architecture switched to generic hard irqs the config
options HAVE_GENERIC_HARDIRQS & GENERIC_HARDIRQS and the related code
for !CONFIG_GENERIC_HARDIRQS can be removed.
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Git-commit: 0244ad004a54e39308d495fee0a2e637f8b5c317
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[imaund@codeaurora.org: resolve merge conflicts]
Signed-off-by: Ian Maund <imaund@codeaurora.org>
Merge support needed for the ARM64 8916 target into msm-3.10.
* origin/tmp-b7dbbd5: (289 commits)
arm: add pdev_archdata for dma_mask
thermal: tsens: fix compilation warning
msm: sps: remove sps header file
defconfig: arm64: msm: enable gpio sysfs reporting
arm64: Align CMA sizes to PAGE_SIZE
msm: ipa: add 64-bit support for IPA
defconfig: msm: Enable IPC Router and QMI kernel interface
msm: kgsl: Implement ioctl_rb_issueibcmds for compat
msm: rndis_ipa: add support for 64 bit
msm: ecm_ipa: add support for 64 bit
ARM: dts: msm: Add SPI clocks for QUP1 on plutonium.
ARM: dts: msm: Configure SPI on plutonium QUP1.
msm: ipa: set dma mask of IPA device
msm: ipa: add support for compat_ioctl
msm: ipa: move out of mach tree
arm: dts: msm8916: Change property for CMA regions
arm64: Change type of dma_{alloc,free}_from_contiguous
msm: kgsl: manage active count for perfcounter read compat ioctl
ion: msm: Add custom compat ioctl
ion: Add custom_compat_ioctl
...
Conflicts:
arch/arm/mach-msm/Kconfig
drivers/platform/msm/ipa/teth_bridge.c
Change-Id: I2e5ebfd104d72a91191fef6de33e107399c17938
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
Make spi_qsd architecture independent by removing
references to mach-msm directory and not assuming
a particular pointer size.
Change-Id: Ie4ccb6ee24b694ba52476a89285c77d7c547502b
Signed-off-by: Dan Sneddon <dsneddon@codeaurora.org>
Data Mover is no longer supported on hardware and removed as dead
code.
Change-Id: Icfbf30e709f7d1ed0ece0eb9c31e4ddb42ac9d5f
Signed-off-by: Dan Sneddon <dsneddon@codeaurora.org>
Message queue is scheduled to process
SPI messages during system suspend
state which leads to crash.
This patch make sure all the messages
in queue are processed before system
suspends.
CRs-Fixed: 593658
Change-Id: I722f24fcee4a1d2bbfee4341c8bc6c36ff9e1ec8
Signed-off-by: Sana Venkat Raju <c_vsana@codeaurora.org>
As part of pinctrl frame work migration, add support
for GPIO configuration using pinctrl frame work.
Now SPI driver supports both pinctrl frame work as
well as GPIO mux to configure GPIO's.
CRs-Fixed: 554189
Change-Id: Ie4232e181705e8c352079fdec882ff4b59bf074f
Signed-off-by: Sana Venkat Raju <c_vsana@codeaurora.org>
Currently SPI driver is queuing a single BAM descriptor
at a time. The BAM engine supports queuing of multiple
transfer descriptors.
Add support to spi driver to queue multiple descriptors.
CRs-Fixed: 546346
Change-Id: Iaee9b3b362832262b75e46e19ad18552d037620b
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
QUP_IRQ complete is triggered before dmov_rx callback.
Which will initiate SPI to start next transfer, due to
this earlier DMOV_CMD is blocked and results in kernel panic.
Current Implementation make sure that transfer complete waits
For DMOV callback only in case of aligned lengths ,This patch
ensures transfer trigger only after DMOV RX call back for
unaligned length also.
CRs-Fixed: 583126
Change-Id: I306a705d0eaf0eac33b2dbf335992254351cce20
Signed-off-by: Sana Venkat Raju <c_vsana@codeaurora.org>
The code paths using remote mutexes are inactive. Remove the dead code.
Change-Id: I99bec429cb18f4b4eb317ccd0ddea807afdd849f
Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
Currently msm_spi_process_message is freeing Chip
Select GPIO only when error occurs instead of
freeing it for every transfer. This patch releases
Chip select GPIO for each transfer complete.
CRs-Fixed: 579737
Change-Id: I3f24fda283714ee8422e42b297f9c10dc3367b65
Signed-off-by: Sana Venkat Raju <c_vsana@codeaurora.org>
Add support to use new message queue feature provided
by SPI core framework. It is having benefits of saving
code space and getting the benefits of improvements
implemented in the core. User can set the priority
of message queue at compile time.
CRs-Fixed: 458268
Change-Id: I3f3a70b20ed6f2c8ceb9c27d616c5ba19acb422c
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
During probe Chip select gpio's valid field is set to non-zero.
This is causing gpio free to get called for not-used gpios
during runtime suspend.
CRs-Fixed: 525743
Change-Id: Ib0de417d640f30908ad11650b584833dac286646
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
Rather than failing the probe function on DMA
initialiation error, this patch just disables DMA
mode and logs an error. The driver continues to
function in FIFO mode.
Change-Id: Ib2532e3497192e1ef7efa02d2dff855826ad6091
Signed-off-by: Gilad Avidov <gavidov@codeaurora.org>
The HW is not mandating the use of input first in bam mode,
therefore, that statement is removed.
CRs-Fixed: 519665
Change-Id: I7c5bbe8a71ea5b8a0e25efdea585251c7c4d4d14
Signed-off-by: Gilad Avidov <gavidov@codeaurora.org>
Sometimes system suspend is initiated before runtime
PM's auto-suspend delay expires and causing devices to
not suspended runtime. As part of system suspend if
device is not suspended runtime then clocks and gpios
are manages by system suspend.
If spi client does initiate transaction request immediately
after system resume then spi doesn't resume run-time
immediately as spi controller's device state is not in
'suspended state'.
Keep device's runtime PM status to suspended during
system suspend.
CRs-Fixed: 512718
Change-Id: I5c0cb39c0b91782d8686c1b3da81125169ccf9be
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
When reading values from the device tree, the error
check on BAM producer pipe must be negated.
Change-Id: Ia766cabdde47390c5a3c79b1c98a704e695fc571
Signed-off-by: Gilad Avidov <gavidov@codeaurora.org>
Redirection on a NULL pointer leads to a system crash.
Here we verify pointers which potentially may be NULL
before a redirection.
Change-Id: I72b856e52f63b13e517c28d8dbb04e1f333f8065
Signed-off-by: Gilad Avidov <gavidov@codeaurora.org>
BAM pipes must be flushed when a transfer timeout
leaving dangling descriptors.
Change-Id: I29fbd2a98964bff5496630a165b3cd0a3f1f2d08
Signed-off-by: Gilad Avidov <gavidov@codeaurora.org>
Currently GPIOs are identified (MISO/MOSI/CLK or CS0..3)
by their index in the device-tree entry's array.
Further, chipselect GPIOs must be declared in order.
This allows to set a value for GPIO number three only
if the values for GPIOs one and two are also set.
This patch allows the driver to identify GPIOs by a
unique name, thus allows to specify any arbitrary
chipselect GPIO and reduces chances of simple
user configuration error.
Change-Id: I7cf1fb4329155bd5fc635257fc58d1dfa7312462
Signed-off-by: Gilad Avidov <gavidov@codeaurora.org>
Due to a bug in the if() condition msm_spi_use_dma
function is always returning '0' when cs_change
is true. Due to this issue the DMA mode is not being used
when it has to be.
CRs-Fixed: 475841
Change-Id: I7da2ee091635f0cfd89058787c35b62adf1984b5
Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
Currently the spi driver votes for its core clock. However, it is
possible that the core-clock's source will be off. When the source
is off, the spi core is not clocked. This patch adds voting for
the entire clock path, thus guarantee clocking to the spi core.
Voting for the path cost a few msecs. A client may choose when
to pay this overhead. By default the votes takes place in the
runtime-pm callbacks which tie to transaction requests. A client
may choose to invoke these callbacks itself whenever it likes
by directly calling the driver's runtime-pm. A third option is
to set the active_only flag in platform data which results in the
callbacks being called when the application processor power state
changes.
CRs-Fixed: 478465
Change-Id: Ib866399c0e84a875a19a0d1506d77bbe77d5fe61
Signed-off-by: Gilad Avidov <gavidov@codeaurora.org>
The SPI mini-core has a specialized signal sampling mode which
improves signal to noise ratio for bus rates that are greater
then or equal to 26MHz.
This patch sets the mini-core in high-speed mode whan
the bus rate is greater or equal to this limit.
CRs-Fixed: 460451
Change-Id: I9a5094c92f3be8b683cd28a7737501d26b45b082
Signed-off-by: Gilad Avidov <gavidov@codeaurora.org>
Enable and disable the clocks and gpios to the SPI controller
using runtime PM. This serves the dual purpose of reducing power
Consumption a little and letting the core know when the device is idle.
If runtime_pm is not supported, then make sure the device becomes
active in first transaction after system-suspend, instead of
system-resume.
CRs-Fixed: 460988
Change-Id: I2360b6f48491cd0e8e5f1ce54805079daf92e36b
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
Updated BAM security setting prohibit direct control of
BAM HW from the execution environment which runs the Kernel.
This patch utilises the BAM's driver support for satellite
-mode which, transparently, controls the BAM from a permitted
execution environment.
Change-Id: I56aab2ba934fa8854fa0202d6766d079f9d0fcb9
Signed-off-by: Gilad Avidov <gavidov@codeaurora.org>
SPI driver doesn't support different block size in
DM mode because based on assumption that GSBI tx&rx
FIFOs are of same size. Some GSBI configuration
can have different tx/rx fifo size. Tx/Rx fifo size
is defined based on input/output block size.
Adds support for different rx/tx fifo size in
case of DMA transaction.
CRs-Fixed: 452986
Change-Id: Ie86f487ea97037ed14e9838a3bd52dfe95f56974
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
Update device tree entries to comply with latest practice.
Change proprietary entry name from "infinite_mode" to
"qcom,infinite-mode" and specify bus-number by alias instead
of "cell-index". The following changes are updated to spi's
device-tree binding document.
CRs-Fixed: 451911
Change-Id: Id54d494c23578315b04e7682fe3a815c7db1b421
Signed-off-by: Gilad Avidov <gavidov@codeaurora.org>
Specifying max clock frequency for SPI, via platform data, requires
a frequency that is available to SPI. The frequencies that are
available to SPI and the devices max-frequency are specified in
different places and in different files. As a result theses values
can easily go out of sync.
SPI devices typically can operate at some maximum frequency, with
some tolerance for the actual-frequency being lower. SPI users
typically know their target-device's max-speed, but they have
to dig in platform data files to find the best matching frequency
that is available.
This patch lets users specify the device's max-frequency, while the
actual frequency is automatically selected by the driver. The selected
frequency is the same as the requested one, or the nearest lower one.
Change-Id: I293ec1b66ad56e4a2b4643482917f79dabd7a758
Signed-off-by: Gilad Avidov <gavidov@codeaurora.org>
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
Client has ability to request delay per transfer through SPI
framework. SPI controller driver needs to put this delay after every
transfer. However, this also means that multiple transfers per message
cannot be combined to be able to insert this delay per transfer.
CS will be de-asserted after completion of each transfer
on older version of QUP/SPI core.
CRs-fixed: 416186
Change-Id: Id9266ce7043e020fa7e1233c66baba30ba3d496c
Signed-off-by: Gilad Avidov <gavidov@codeaurora.org>
Signed-off-by: Sagar Dharia <sdharia@codeaurora.org>
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
Call the dma_teardown callback on the error path only if
one has been registered.
Change-Id: I9c5c9d59ea504be9417be089d6d3055a230a482f
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
The new SPI QUP-core version-2, adds support to a new DMA
engine, adds a new register, and introduces some changes to
existing registers. The new BAM DMA engine supersedes the
older Data-Mover DMA engine. The new register, the hardware-
version register, is used by the patch to query the hardware
about its precise version. Using the precise version the driver
may verify HW support for the BAM mode.
This patch keeps backward compatibility with older
Qualcomm SPI-controllers exisiting in and QUP-core-ver-1 and
pre-QUP cores. The new QUP-core-ver-2 features three transfer
modes each optimized for a different transfer size: FIFO-mode for
small transfers, Block-mode for mid-size transfers, and BAM mode
for large size transfers. The current SPI driver supports only FIFO
mode. This mode is utilized for transfers of all sized. This patch
enables BAM-mode for mid to large size transfers. Using of the
BAM engine for large transfers, reliefs the CPU of slow IO
operations.
The patch relies on new platform-specific-data entries to read
values for BAM configuration.
Change-Id: I8baa89e6e33197c6265ab7f38965e7c3e10e80f8
Signed-off-by: Gilad Avidov <gavidov@codeaurora.org>
Configure the spi clk, mosi, miso, cs gpio's on per
transaction basis and unconfigure otherwise.
It will remove the conflicts if same gpio's are
being used by different modules if no SPI device
is present.
CRs-Fixed: 387043
Change-Id: Ib5c3bfbd13681f4aee0c4a815b19f423c586e160
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
Support to transfer 64K bytes in a single SPI
transfer in DMA mode on targets which support
16 bits in QUP_MX_OUTPUT_CNT register. Earlier
if the application sends more than 4K data it is
split up in to 4K chunks, irrespective of the size
of the QUP_MX_OUTPUT_CNT register.
CRs-Fixed: 383120
Change-Id: Ibbe73df2bb4fb2804ff6ebfc62adac9d0d53e9cd
Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
When using device tree, the bus number needs to be set based on the
cell-index property rather than the 'id' from the platform device.
This makes sure that the SPI bus number is set correctly.
Change-Id: I4489c28363a7fd79f3bc3db76207a1bc8ef507cb
Signed-off-by: Kenneth Heitke <kheitke@codeaurora.org>
If infinite mode is not supported, chip select goes
high after every 4k bytes. Make sure the same behavior
does not happen on targets that support infinite mode.
CRs-Fixed: 361961
Change-Id: I5cfea96202718214a8edd060e06fbb7fb2fa90a2
Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
The spidev module is not being removed cleanly since
the SPI device is not being unregistered.
Change-Id: I1f97163b3eef585b420a474cdd2aacc7657e6254
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
Change-Id: I4d5d611a64d8fac4c643e8eb454056ab939eff99
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
Adding a seperate rx buffer for spidev. This allows errors
in transmission to be noticed.
Change-Id: I02258bccf1a4a5543b94c30f51294185498c3c40
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
Adding parameters to spidev module, to allow it to be
added dynamically to the SPI bus. This allows a test
application to insmod it whenever needed and test the
SPI core.
Change-Id: Ifdb7b0c7a67f58d46ebcdc1032f0a654b6c53080
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
Including the following patches:
commit 0f7723bb09440ae69743fed38cf558a838aa9bdf
Author: Bryan Huntsman <bryanh@codeaurora.org>
Date: Thu Oct 6 23:13:56 2011 -0700
Revert "spi_qsd: GPIO configuration changes for SPI chip-select line"
This reverts commit 7eaa08b75995289a91c7dd1f3616f79227f5f923.
Signed-off-by: Bryan Huntsman <bryanh@codeaurora.org>
commit 7eaa08b75995289a91c7dd1f3616f79227f5f923
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Wed Sep 28 16:26:39 2011 -0600
spi_qsd: GPIO configuration changes for SPI chip-select line
The chip-select GPIO's pertaining to each slave remains in suspended
configuration until the first transfer is intiated by the slave.
Change-Id: I3aa8555289be7ce457b91a969cf03909be0965d7
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit e47df9f9b932968152ab2908153e60adab4402d7
Author: Jordan Crouse <jcrouse@codeaurora.org>
Date: Mon Sep 19 11:21:16 2011 -0600
spi_qsd: Fix possible uninitialized variable
Change-Id: Ic0dedbad184046e9835cde015ad5d592f33e82a6
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
commit 4ae02c76b98f2b96bfb8c4fa02f40cfda2f16f97
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Tue Sep 20 17:28:50 2011 -0600
spi_qsd: Fix Klocwork errors in SPI driver
Change-Id: I1fe6632e68ea625966aced37a1b140b30534e101
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit 52e065ba3d86977b59937693ac7e85836cf4eca8
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Thu Sep 1 12:12:58 2011 -0600
spi_qsd: Fix for SPI Operational State Invalid error
This error is reproted randomly when the SPI core is put
into RUN state and occurs when the ACPU clock is low.
When the timer expires, we check again to ensure that the
STATE_VALID bit is set before returning.
Change-Id: Ic8912534f4924efd999b8aa1d75a9fd19749e870
CRs-fixed: 304672
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit a9a8816913e5466e06b443c42cbf8ae866b95fd1
Author: Jeff Ohlstein <johlstei@codeaurora.org>
Date: Fri Sep 2 13:55:16 2011 -0700
msm: dma: remove crci conflict checking
The crci conflict checking code was designed for a system where a crci's
mux could be changed at runtime. In reality, our chips configure these
statically, so it is not necessary.
Change-Id: I4d5f32cd8728d3c78fca8f64aed0e02b57b6afba
Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org>
commit 36c6f1bb48af3e65db281cc7ccb913a8e81a598e
Author: Matt Wagantall <mattw@codeaurora.org>
Date: Wed Aug 17 15:44:58 2011 -0700
msm: clock: Rename all I2C/SPI clocks to 'core_clk' or "iface_clk"
Drivers should now use their device names to distinguish between
clocks of the same type rather than the clock name.
Change-Id: Iab12caf4eab163773d68f1b2adc1bb4c72c69e83
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
commit 55e656e68cac78eaa367341df2e693a483a53f84
Author: Stepan Moskovchenko <stepanm@codeaurora.org>
Date: Mon Jun 6 14:34:38 2011 -0700
drivers: barriers: Replace dsb() with mb()
Replace explicit dsb() calls with mb(). Now that the
generic ARM implementation defines mb() to mean (at least)
dsb(), it is appropriate to switch back to the generic
kernel version of the barriers. This is also needed for
correctness on certain targets (such as 7x27) where dsb()
is insufficient and other operations (such as outer cache
sync or writing to strongly-ordered memory) are required to
ensure proper I/O operations ordering. In some cases,
remove explicit calls to outer_sync following a barrier
since the barrier will now have an explicit outer_sync
call.
Change-Id: I2c53b8534af9c3cbac4d4d77b322f897a39e7758
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
commit 17194a32164b868f80ce84e313f9148d1dc77e7b
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Fri Jun 3 18:10:09 2011 -0600
spi_qsd: GPIO configuration changes
On suspend, the SPI related GPIO's enter a low power configuration
and on resume they move to an active configuration. This helps
conserving power during power collapse.
Change-Id: I0911867e10fadcfc6950f6dddf74226bd6321c16
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit 1777d88688511cd59bad7674c6a2246e0c93142b
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Wed Jun 1 16:54:07 2011 -0600
spi_qsd: Remove restriction on SPI clock speed.
When multiple slaves are connected to the SPI controller,
the driver does not allow the clock to go from lower speed
to a higher speed. This restriction is not required since
there can only be one slave listening at a time. Also,
there are no hardware limitations in doing so.
Change-Id: I4ecabfb3a1515416f050c18678cf0987dcde9d1e
CRs-fixed: 290127
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit 4b7c7bfc546cb02141da9d034421aefe5635f857
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Tue Jun 7 14:18:42 2011 -0600
spi_qsd: Add null pointer check before dereferencing
During probe, there is no cur_msg to set the status.
Change-Id: I82e00b9d74d45c36b70078b171db1bb150d1bfac
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit bf514c766fcc2bdee680f80a2ea16c7fead0be96
Author: Stepan Moskovchenko <stepanm@codeaurora.org>
Date: Mon May 16 13:37:11 2011 -0700
msm: spi: Fix access to unclocked registers
Don't program the GSBI configuration until the clocks have
been turned on.
Change-Id: Idee5f5dffcb5ed0f7de18f1e508ee8c76b618894
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
commit d9c248213f4cd025f3d3586f0de81e4bc44a5a54
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Mon May 16 16:43:08 2011 -0600
spi_qsd: Fix for SPI input overrun error
This error occurs due to a bug in the controller.
This bogus error is reported when a transition from run
to reset state occurs and if the input FIFO has an odd number
of entries.
Change-Id: I555864d4855ac6d416997da69d8bc6aee7a82178
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit e99ceb5b3da7bec51be853809c25df8e32b2c1e6
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Thu Apr 14 18:36:34 2011 -0600
spi_qsd: Multi-transfer handling
When there are mulitple SPI transfers in a message, we
default to using FIFO mode for all the transfers. As special
case, we handle a WR-WR or WR-RD transfer where we choose
between FIFO mode and DM mode based on the total length of
the transaction.
Change-Id: I6fbc1a06a22f9782db5b97c9b87cc53392a8c2fa
CRs-fixed: 276666
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit 8f3d3aaa51603a929027bc820fe2d3515e959779
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Tue Apr 19 14:19:29 2011 -0600
spi_qsd: Ensure IO operation ordering
Adding memory barriers to ensure that the writes and reads
to the SPI and QUP registers happen in the correct order.
Change-Id: I86d8f63b0e9547a2339ee4ab5c713cf8864fef04
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit 36b3fae5f54230cd1e4ca072d1f55cb2f79d8945
Author: Laura Abbott <lauraa@codeaurora.org>
Date: Thu Oct 14 12:48:16 2010 -0700
spi_qsd: Fix section mismatch
The function msm_spi_probe is referenced outside of the __init section.
This fixes the problem by calling platform_driver_probe instead of
platform_driver_register since this device is not hotplugable.
Change-Id: I3a563c6fc562ada959317b54ff60a38f9ce517d8
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
commit dc2e36eecefb6628031afeff28afd9d97f2f3f6f
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Wed Sep 29 16:58:20 2010 -0600
spi_qsd: Changes to support DM mode.
The dma_config function may not always be present.
This change makes sure the driver gets DM resources
irrespective of the dma_config function.
Change-Id: I25a2497d20e973f22b76f2b5d6f68c86bd4d5f1d
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit a39bd4a398674c320925540eec91d94d2b7d53f3
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Thu Aug 19 17:48:01 2010 -0600
spi_qsd: Modify timeout mechanism to check SPI state valid bit.
In order to allow sufficient time for the SPI state
transition to occur, calculate the timeout based on
the SPI clock speed.
Change-Id: I3d6955b2a64a8bf8980590e352fbd564250210fb
CRs-fixed: 250998
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit b5887b644ba9545672d637985713c7e0e2e5bb50
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Tue Aug 3 16:57:33 2010 -0600
spi_qsd: Use FIFO mode when DM mode configuration fails.
When the Data Mover configuration fails, the driver
uses FIFO mode.
Change-Id: Iaf83e50fe725654c58260c5cd1150cdeb56f51c8
CRs-fixed: 249238
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit ced8ad320d480006643a3aa3474f5c0d77457454
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Mon Jun 28 16:01:33 2010 -0600
spi_qsd: Use SW timeout instead of SPI_TIME_OUT register.
Since the software timeout is already present in the driver,
the hardware SPI_TIME_OUT register is being removed.It is just
redundant and used only for debugging purposes.
Change-Id: I829cb944444fc3e5053bc810adffe2b87f511b63
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit 35e9155f59317e8ef63b8ce5190f26f5cae6a8ee
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Fri Jun 25 16:48:25 2010 -0600
spi_qsd: Disable irqs in the probe function.
The irqs are disabled at all times in the probe function
irrespective of the use of remote lock.
Change-Id: I0997d07b93c97a12bca6d80a9bba59682b1bec3e
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit e6af92d74a35ba267125bc61c2c6c18034c03af3
Author: Harini Jayaraman <harinij@codeaurora.org>
Date: Tue Jun 22 12:20:46 2010 -0600
spi_qsd: Disable clocks and irqs when SPI bus is not in use.
The SPI clocks and irqs are enabled per workqueue and correspondingly
disabled once the workqueue is completed.
Change-Id: Ib22b7e3b946eb4c829940e43327caaf5aff7721b
CRs-fixed: 242866
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
commit b25e4220efdacc231cb150fc263af1e3f525b165
Author: Lena Salman <esalman@qualcomm.com>
Date: Tue Jun 8 15:25:47 2010 +0300
spi_qsd: Add usage of MX_WRITE_COUNT register
Use MX_WRITE_COUNT register to reduce the amount of TX interrupts in
FIFO mode for transfers smaller than FIFO size.
Change-Id: I7208fdc85b626a31a8b781ee5c56f73beee6c427
Signed-off-by: Lena Salman <esalman@qualcomm.com>
commit 7ed56f3441c5ebe7fd8107fb8468207a88bc743f
Author: Lena Salman <esalman@qualcomm.com>
Date: Wed Jun 9 16:14:44 2010 +0300
spi_qsd: Minor changes to support Data Mover mode on QUPe core
Minor changes to support Data Mover made on QUPe core.
Change-Id: I54663115a43f7fd9b52a2ddee796b5499d5f239a
Signed-off-by: Lena Salman <esalman@qualcomm.com>
commit a85fd0ab6484eb2ef404c062adffce1ee22337f1
Author: Lena Salman <esalman@qualcomm.com>
Date: Thu Jun 3 13:57:02 2010 +0300
spi_qsd: Add support for QUPe controller
QUPe controller is a new version of Qualcomm SPI controller. The
controller also supports other peripheral protocols, however its SPI
functionality is very similar to previous SPI core, supported by spi_qsd.
Therefore the same driver is being utilized with some register address
modification and minor flow change.
Change-Id: Ic091ef2c2ed699b43f786c278b613e69a7e9039b
Signed-off-by: Lena Salman <esalman@qualcomm.com>
commit ce270f6f9198cf40ee5638b35e595da81116241e
Author: Jeff Ohlstein <johlstei@quicinc.com>
Date: Thu Apr 29 13:40:53 2010 -0700
drivers: spi: Support ADM3 in spi_qsd driver
Change-Id: I6dfa38a4c33a8e4619d56ce30787e1aeafc8356d
Signed-off-by: Jeff Ohlstein <johlstei@quicinc.com>
commit 47346fa611773ef92d12d9145ea33a7f2c79052f
Author: Lena Salman <esalman@qualcomm.com>
Date: Wed Apr 28 11:33:15 2010 +0300
spi_qsd: Add disable/enable of pclk to suspend/resume functions
Add disable/enable of pclk to suspend/resume functions to improve
power performance.
Change-Id: I871e5ac90a998f2942778bb1e8c2c9d583a9ae00
CRs-fixed: 235046
Signed-off-by: Lena Salman <esalman@qualcomm.com>
commit a96eba98fbbd21ac657f5d551466909352766ead
Author: Lena Salman <esalman@qualcomm.com>
Date: Sun Apr 11 10:40:37 2010 +0300
spi_qsd: Making irq code implicit for the core mode in use
Make code clear regarding what mode is in use in the irq.
Signed-off-by: Lena Salman <esalman@qualcomm.com>
commit 6a02d85f8f48cf6f86cddc38c9fce9c1179208b4
Author: Lena Salman <esalman@qualcomm.com>
Date: Tue Apr 13 21:16:45 2010 +0300
spi_qsd: Separate tx/rx/error statistics between contexts
To improve SMP safety, separate the tx/error statistics between
contexts. This protects the statistics from accidentally being
access from another context at the same time.
Change-Id: Ibc52406e7b06a4bb5142f8a09a2f35442cb9df8a
Signed-off-by: Lena Salman <esalman@qualcomm.com>
commit 31f301c171aab8e42f8b6abe9b7866412cb546a8
Author: Lena Salman <esalman@qualcomm.com>
Date: Tue Mar 23 14:51:00 2010 +0200
spi_qsd: Add better handling for pending transfers during suspend
To improve SMP safety, add better handling in suspend function to wait
for graceful closure of pending transfers. This graceful closure waits
for all the pending transfers to finish or timeout, while not allowing new
ones to queue up. This allows correct handling of all the resources
involved in a transfer before suspend.
Signed-off-by: Lena Salman <esalman@qualcomm.com>
commit 8fbf6e4c5371520b5f9de2001e2ebd15773e918b
Author: Lena Salman <esalman@qualcomm.com>
Date: Thu Mar 25 10:44:10 2010 +0200
spi_qsd: Add mutex to get exclusive access to controller registers
To improve SMP safety, add mutex to get exclusive access to controller
registers.
Signed-off-by: Lena Salman <esalman@qualcomm.com>
commit 9405adda67d8c6a856243e599f09d806b4bc6de5
Author: Kenneth Heitke <kheitke@quicinc.com>
Date: Thu Apr 15 16:33:16 2010 -0600
spi_qsd: Move global input_fifo_size to device context.
Fix reference to device data input_fifo_size which is missing from the
previous patch.
Change-Id: Ia469896edd0fd90d7ded2b8ec44f9075474b3ec8
Signed-off-by: Kenneth Heitke <kheitke@quicinc.com>
commit 6031094ca6a940a47437bc6a092e813b4bc41d2a
Author: Lena Salman <esalman@qualcomm.com>
Date: Sun Apr 11 10:34:48 2010 +0300
spi_qsd: Move global input_fifo_size to device context.
To improve SMP safety move global variable input_fifo_size to device
context.
Signed-off-by: Lena Salman <esalman@qualcomm.com>
commit 97f585033413b1f8ae210bbffd617a4af3462982
Author: Lena Salman <esalman@qualcomm.com>
Date: Wed Apr 14 18:35:54 2010 +0300
spi_qsd: Initial contribution of the MSM SPI driver
This adds MSM SPI controller driver. The driver is SPI master, and
allows slave connections. Current version of the driver supports
FIFO and DM modes chosen upon the message size. The driver also
supports loopback mode which can be used for testing purposes.
This is a squashed version of all the MSM SPI driver changes on the QuIC
MSM 2.6.29 kernel which can be found at www.codeaurora.org.
It also contains all relevant adaptations to SPI core changes in 2.6.32
kernel.
https://www.codeaurora.org/gitweb/quic/la/?p=kernel/msm.git;a=blob;f=drivers/spi/spi_qsd.c;h=1c8e3ec727b29040648ef9a4949396f7109528ae;hb=refs/heads/android-msm-2.6.29b
Change-Id: Ibc1e71deb662af87deed77f10dcc8a3a46a8f012
Signed-off-by: Lena Salman <esalman@qualcomm.com>
Signed-off-by: David Brown <davidb@codeaurora.org>
commit 89c66ee890af18500fa4598db300cc07c267f900 upstream.
Commit 048177ce3b (spi: spi-davinci:
convert to DMA engine API) introduced a regression: dma_map_single()
is called with direction DMA_FROM_DEVICE for rx and for tx.
Signed-off-by: Christian Eggers <ceggers@gmx.de>
Acked-by: Matt Porter <mporter@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
pxa2xx_spi_map_dma_buffer() gets called in tasklet context so we can't
sleep when we allocate a new sg table. Use GFP_ATOMIC here instead.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Cc: stable@vger.kernel.org
If the device is already in a runtime PM enabled state
pm_runtime_get_sync() will return 1, so a test for negative
value should be used to check for errors.
Without this patch there are seen errors like:
[ 8.540000] s3c64xx-spi 13930000.spi: Failed to enable device: 1
[ 8.545000] spi_master spi1: failed to prepare transfer hardware
Likely because the driver uses synchronous API to runtime enable
the device and asynchronous one to disable it.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Mark Brown <broonielinaro.org>
Cc: stable@vger.kernel.org
Current HSPI driver is using msleep(20) on hspi_status_check_timeout(),
but it was too long delay for SPI device.
Bock-W board SPI access was too slow without this patch.
This patch uses udelay(10) for it.
Tested-by: Yusuke Goda <yusuke.goda.sx@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
The ISR currently consumes the rx buffer data and re-enables transmission
from within interrupt context. This is bad because if the interrupt
occurs again before the ISR exits, the new interrupt will be erroneously
cleared by the still completing ISR.
Simplified the ISR by just setting the completion variable and exiting with
no action. Then just looped the transmit functionality in
xilinx_spi_txrx_bufs().
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Fix to return -ENOMEM in the platform_device_alloc() error handling
case instead of 0, as done elsewhere in this function.
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
free_irq() expects the same pointer that was passed to request_irq(), otherwise
the IRQ is not freed.
The issue was found using the following coccinelle script:
<smpl>
@r1@
type T;
T devid;
@@
request_irq(..., devid)
@r2@
type r1.T;
T devid;
position p;
@@
free_irq@p(..., devid)
@@
position p != r2.p;
@@
*free_irq@p(...)
</smpl>
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Pull devm usage cleanup from Wolfram Sang:
"Lately, I have been experimenting how to improve the devm interface to
make writing device drivers easier and less error prone while also
getting rid of its subtle issues. I think it has more potential but
still needs work and definately conistency, especiall in its usage.
The first thing I come up with is a low hanging fruit regarding
devm_ioremap_resouce(). This function already checks if the passed
resource is valid and gives an error message if not. So, we can
remove similar checks from the drivers and get rid of a bit of code
and a number of inconsistent error strings.
This series only removes the unneeded check iff devm_ioremap_resource
follows platform_get_resource directly. The previous version tried to
shuffle code if needed, too, what lead to an embarrasing bug. It
turned out to me that shuffling code for all cases found will make the
automated script too complex, so I am unsure if an automated cleanup
is the proper tool for this case. Removing the easy stuff seems
worthwhile to me, though.
Despite various architectures and platform dependencies, I managed to
compile test 45 out of 57 modified files locally using heuristics and
defconfigs."
Pulled because: 296 deletions, 0 additions.
* 'devm_no_resource_check' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: (33 commits)
sound/soc/kirkwood: don't check resource with devm_ioremap_resource
sound/soc/fsl: don't check resource with devm_ioremap_resource
arch/mips/lantiq/xway: don't check resource with devm_ioremap_resource
arch/arm/plat-samsung: don't check resource with devm_ioremap_resource
arch/arm/mach-tegra: don't check resource with devm_ioremap_resource
drivers/watchdog: don't check resource with devm_ioremap_resource
drivers/w1/masters: don't check resource with devm_ioremap_resource
drivers/video/omap2/dss: don't check resource with devm_ioremap_resource
drivers/video/omap2: don't check resource with devm_ioremap_resource
drivers/usb/phy: don't check resource with devm_ioremap_resource
drivers/usb/host: don't check resource with devm_ioremap_resource
drivers/usb/gadget: don't check resource with devm_ioremap_resource
drivers/usb/chipidea: don't check resource with devm_ioremap_resource
drivers/thermal: don't check resource with devm_ioremap_resource
drivers/staging/nvec: don't check resource with devm_ioremap_resource
drivers/staging/dwc2: don't check resource with devm_ioremap_resource
drivers/spi: don't check resource with devm_ioremap_resource
drivers/rtc: don't check resource with devm_ioremap_resource
drivers/pwm: don't check resource with devm_ioremap_resource
drivers/pinctrl: don't check resource with devm_ioremap_resource
...
devm_ioremap_resource does sanity checks on the given resource. No need to
duplicate this in the driver.
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
GENERIC_GPIO now synonymous with GPIOLIB. There are no longer any valid
cases for enableing GENERIC_GPIO without GPIOLIB, even though it is
possible to do so which has been causing confusion and breakage. This
branch does the work to completely eliminate GENERIC_GPIO.
However, it is not trivial to just create a branch to remove it. Over
the course of the v3.9 cycle more code referencing GENERIC_GPIO has been
added to linux-next that conflicts with this branch. The following must
be done to resolve the conflicts when merging this branch into mainline:
* "git grep CONFIG_GENERIC_GPIO" should return 0 hits. Matches should be
replaced with CONFIG_GPIOLIB
* "git grep '\bGENERIC_GPIO\b'" should return 1 hit in the Chinese
documentation.
* Selectors of GENERIC_GPIO should be turned into selectors of GPIOLIB
* definitions of the option in architecture Kconfig code should be deleted.
Stephen has 3 merge fixup patches[1] that do the above. They are currently
applicable on mainline as of May 2nd.
[1] http://www.mail-archive.com/linux-kernel@vger.kernel.org/msg428056.html
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Merge tag 'gpio-for-linus' of git://git.secretlab.ca/git/linux
Pull removal of GENERIC_GPIO from Grant Likely:
"GENERIC_GPIO now synonymous with GPIOLIB. There are no longer any
valid cases for enableing GENERIC_GPIO without GPIOLIB, even though it
is possible to do so which has been causing confusion and breakage.
This branch does the work to completely eliminate GENERIC_GPIO."
* tag 'gpio-for-linus' of git://git.secretlab.ca/git/linux:
gpio: update gpio Chinese documentation
Remove GENERIC_GPIO config option
Convert selectors of GENERIC_GPIO to GPIOLIB
blackfin: force use of gpiolib
m68k: coldfire: use gpiolib
mips: pnx833x: remove requirement for GENERIC_GPIO
openrisc: default GENERIC_GPIO to false
avr32: default GENERIC_GPIO to false
xtensa: remove explicit selection of GENERIC_GPIO
sh: replace CONFIG_GENERIC_GPIO by CONFIG_GPIOLIB
powerpc: remove redundant GENERIC_GPIO selection
unicore32: default GENERIC_GPIO to false
unicore32: remove unneeded select GENERIC_GPIO
arm: plat-orion: use GPIO driver on CONFIG_GPIOLIB
arm: remove redundant GENERIC_GPIO selection
mips: alchemy: require gpiolib
mips: txx9: change GENERIC_GPIO to GPIOLIB
mips: loongson: use GPIO driver on CONFIG_GPIOLIB
mips: remove redundant GENERIC_GPIO select
These are cleanups and smaller changes that either depend on earlier
feature branches or came in late during the development cycle.
We normally try to get all cleanups early, so these are the exceptions:
- A follow-up on the clocksource reworks, hopefully the last time
we need to merge clocksource subsystem changes through arm-soc.
A first set of patches was part of the original 3.10 arm-soc cleanup
series because of interdependencies with timer drivers now moved out
of arch/arm.
- Migrating the SPEAr13xx platform away from using auxdata for DMA
channel descriptions towards using information in device tree,
based on the earlier SPEAr multiplatform series
- A few follow-ups on the Atmel SAMA5 support and other changes
for Atmel at91 based on the larger at91 reworks.
- Moving the armada irqchip implementation to drivers/irqchip
- Several OMAP cleanups following up on the larger series already
merged in 3.10.
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Merge tag 'cleanup-for-linus-2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC late cleanups from Arnd Bergmann:
"These are cleanups and smaller changes that either depend on earlier
feature branches or came in late during the development cycle. We
normally try to get all cleanups early, so these are the exceptions:
- A follow-up on the clocksource reworks, hopefully the last time we
need to merge clocksource subsystem changes through arm-soc.
A first set of patches was part of the original 3.10 arm-soc
cleanup series because of interdependencies with timer drivers now
moved out of arch/arm.
- Migrating the SPEAr13xx platform away from using auxdata for DMA
channel descriptions towards using information in device tree,
based on the earlier SPEAr multiplatform series
- A few follow-ups on the Atmel SAMA5 support and other changes for
Atmel at91 based on the larger at91 reworks.
- Moving the armada irqchip implementation to drivers/irqchip
- Several OMAP cleanups following up on the larger series already
merged in 3.10."
* tag 'cleanup-for-linus-2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (50 commits)
ARM: OMAP4: change the device names in usb_bind_phy
ARM: OMAP2+: Fix mismerge for timer.c between ff931c82 and da4a686a
ARM: SPEAr: conditionalize SMP code
ARM: arch_timer: Silence debug preempt warnings
ARM: OMAP: remove unused variable
serial: amba-pl011: fix !CONFIG_DMA_ENGINE case
ata: arasan: remove the need for platform_data
ARM: at91/sama5d34ek.dts: remove not needed compatibility string
ARM: at91: dts: add MCI DMA support
ARM: at91: dts: add i2c dma support
ARM: at91: dts: set #dma-cells to the correct value
ARM: at91: suspend both memory controllers on at91sam9263
irqchip: armada-370-xp: slightly cleanup irq controller driver
irqchip: armada-370-xp: move IRQ handler to avoid forward declaration
irqchip: move IRQ driver for Armada 370/XP
ARM: mvebu: move L2 cache initialization in init_early()
devtree: add binding documentation for sp804
ARM: integrator-cp: convert use CLKSRC_OF for timer init
ARM: versatile: use OF init for sp804 timer
ARM: versatile: add versatile dtbs to dtbs target
...
These are mostly new device tree bindings for existing drivers, as well
as changes to the device tree source files to add support for those
devices, and a couple of new boards, most notably Samsung's Exynos5
based Chromebook.
The changes depend on earlier platform specific updates and touch
the usual platforms: omap, exynos, tegra, mxs, mvebu and davinci.
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Merge tag 'dt-for-linus-2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC device tree updates (part 2) from Arnd Bergmann:
"These are mostly new device tree bindings for existing drivers, as
well as changes to the device tree source files to add support for
those devices, and a couple of new boards, most notably Samsung's
Exynos5 based Chromebook.
The changes depend on earlier platform specific updates and touch the
usual platforms: omap, exynos, tegra, mxs, mvebu and davinci."
* tag 'dt-for-linus-2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (169 commits)
ARM: exynos: dts: cros5250: add EC device
ARM: dts: Add sbs-battery for exynos5250-snow
ARM: dts: Add i2c-arbitrator bus for exynos5250-snow
ARM: dts: add mshc controller node for Exynos4x12 SoCs
ARM: dts: Add chip-id controller node on Exynos4/5 SoC
ARM: EXYNOS: Create virtual I/O mapping for Chip-ID controller using device tree
ARM: davinci: da850-evm: add SPI flash support
ARM: davinci: da850: override SPI DT node device name
ARM: davinci: da850: add SPI1 DT node
spi/davinci: add DT binding documentation
spi/davinci: no wildcards in DT compatible property
ARM: dts: mvebu: Convert mvebu device tree files to 64 bits
ARM: dts: mvebu: introduce internal-regs node
ARM: dts: mvebu: Convert all the mvebu files to use the range property
ARM: dts: mvebu: move all peripherals inside soc
ARM: dts: mvebu: fix cpus section indentation
ARM: davinci: da850: add EHRPWM & ECAP DT node
ARM/dts: OMAP3: fix pinctrl-single configuration
ARM: dts: Add OMAP3430 SDP NOR flash memory binding
ARM: dts: Add NOR flash bindings for OMAP2420 H4
...
This is support for the ARM Chromebook, originally scheduled
as a "late" pull request. Since it's already late now, we
can combine this into the existing next/dt2 branch.
* late/dt:
ARM: exynos: dts: cros5250: add EC device
ARM: dts: Add sbs-battery for exynos5250-snow
ARM: dts: Add i2c-arbitrator bus for exynos5250-snow
ARM: dts: Add chip-id controller node on Exynos4/5 SoC
ARM: EXYNOS: Create virtual I/O mapping for Chip-ID controller using device tree
Fix using PIO transfer mode only support 8 bits transfer, doesn't support 16 bits.
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
[wenyou.yang@atmel.com: submit the patch]
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
A fairly quiet release for SPI, mainly driver work. A few highlights:
- Supports bits per word compatibility checking in the core.
- Allow use of the IP used in Freescale SPI controllers outside
Freescale SoCs.
- DMA support for the Atmel SPI driver.
- New drivers for the BCM2835 and Tegra114.
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Merge tag 'spi-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi updates from Mark Brown:
"A fairly quiet release for SPI, mainly driver work. A few highlights:
- Supports bits per word compatibility checking in the core.
- Allow use of the IP used in Freescale SPI controllers outside
Freescale SoCs.
- DMA support for the Atmel SPI driver.
- New drivers for the BCM2835 and Tegra114"
* tag 'spi-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (68 commits)
spi-topcliff-pch: fix to use list_for_each_entry_safe() when delete list items
spi-topcliff-pch: missing platform_driver_unregister() on error in pch_spi_init()
ARM: dts: add pinctrl property for spi node for atmel SoC
ARM: dts: add spi nodes for the atmel boards
ARM: dts: add spi nodes for atmel SoC
ARM: at91: add clocks for spi dt entries
spi/spi-atmel: add dmaengine support
spi/spi-atmel: add flag to controller data for lock operations
spi/spi-atmel: add physical base address
spi/sirf: fix MODULE_DEVICE_TABLE
MAINTAINERS: Add git repository and update my address
spi/s3c64xx: Check for errors in dmaengine prepare_transfer()
spi/s3c64xx: Fix non-dmaengine usage
spi: omap2-mcspi: fix error return code in omap2_mcspi_probe()
spi/s3c64xx: let device core setup the default pin configuration
MAINTAINERS: Update Grant's email address and maintainership
spi: omap2-mcspi: Fix transfers if DMADEVICES is not set
spi: s3c64xx: move to generic dmaengine API
spi-gpio: init CS before spi_bitbang_setup()
spi: spi-mpc512x-psc: let transmiter/receiver enabled when in xfer loop
...
Since we will remove items off the list using list_del_init() we need
to use a safe version of the list_for_each_entry() macro aptly named
list_for_each_entry_safe().
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: Mark Brown <broonie@sirena.org.uk>
Add the missing platform_driver_unregister() before return
from pch_spi_init() in the error handling case.
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Add dmaengine support.
Using "has_dma_support" member of struct is used to select
the transfer mode: dmaengine or pdc.
For the dmaengine transfer mode, it supports both 8 bits and 16 bits transfer.
For the dmaengine transfer mode, if it fails to config dmaengine,
or if the message length is less than 16 bytes, it will use the PIO transfer mode.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
[wenyou.yang@atmel.com: using "has_dma_support" to select dmaengine as the spi xfer mode]
[wenyou.yang@atmel.com: fix DMA: OOPS if buffer > 4096 bytes]
[wenyou.yang@atmel.com: submit the patch]
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
[richard.genoud@gmail.com: update with dmaengine interface]
[richard.genoud@gmail.com: fix __init/__devinit sections mismatch]
[richard.genoud@gmail.com: adapt to slave_config changes]
[richard.genoud@gmail.com: add support t0 16 bits transfer]
Tested-by: Richard Genoud <richard.genoud@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Will allow to drop the lock during DMA operations.
Replacing non-irqsave versions with irqsave versions of the lock
to make it correct in both pdc and dmaengine transfer mode
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
[wenyou.yang@atmel.com: submit the patch]
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Richard Genoud <richard.genoud@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Needed for future use with dmaengine enabled driver.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
[wenyou.yang@atmel.com: submit the patch]
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Richard Genoud <richard.genoud@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This fixes building the spi-sirf driver as a loadable module, which uses
an incorrect MODULE_DEVICE_TABLE, by changing the reference to the
correct symbol.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This is a series originally prepared for inclusion in 3.9, which did
not work out because of dependencies on the dmaengine driver. All the
changes for the dmaengine code are merged in 3.9 now, so we can finally
do the switchover and remove the now unnecessary dma definitions for
spear13xx from the platform code.
The dma platform_data actually made up the majority of the spear13xx
platform code overall, so moving that into device tree files makes the
code substantially smaller.
* spear/dwdma:
ata: arasan: remove the need for platform_data
ARM: SPEAr13xx: Pass generic DW DMAC platform data from DT
serial: pl011: use generic DMA slave configuration if possible
spi: pl022: use generic DMA slave configuration if possible
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The multiplatform conversion in commit 788437 (spi: s3c64xx: move to
generic dmaengine API) tested for the use of the Samsung-specific DMA
API with SAMSUNG_DMADEV when in fact S3C_DMA should be used. This
renderd DMA based transfers non-functional on platforms not using
dmaengine.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Fix to return a negative error code from the error handling
case instead of 0, as returned elsewhere in this function.
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This set of patches adds support for PWMs and SPI
controller present on DA850 and for SPI flash present on
DA850 EVM.
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Merge tag 'davinci-for-v3.10/dt-2-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/dt2
From Sekhar Nori:
v3.10 DT updates for DaVinci
This set of patches adds support for PWMs and SPI
controller present on DA850 and for SPI flash present on
DA850 EVM.
* tag 'davinci-for-v3.10/dt-2-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
ARM: davinci: da850-evm: add SPI flash support
ARM: davinci: da850: override SPI DT node device name
ARM: davinci: da850: add SPI1 DT node
spi/davinci: add DT binding documentation
spi/davinci: no wildcards in DT compatible property
ARM: davinci: da850: add EHRPWM & ECAP DT node
ARM: davinci: da850: override mmc DT node device name
ARM: davinci: da850: add mmc DT entries
mmc: davinci_mmc: add DT support
ARM: davinci: da850: add tps6507x regulator DT data
ARM: regulator: add tps6507x device tree data
ARM: davinci: remove test for undefined Kconfig macro
ARM: davinci: mmc: derive version information from device name
ARM: davinci: da850: add ECAP & EHRPWM clock nodes
ARM: davinci: clk framework support for enable/disable functionality
Signed-off-by: Olof Johansson <olof@lixom.net>
Follow DT naming convention for compatible property of the blob.
Use first chip name that introduced the specific version of the
device.
Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
With device core now able to setup the default pin configuration,
the pin configuration code based on the deprecated Samsung specific
gpio bindings is removed.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Grant Likely <grant.likely@linaro.org>
GENERIC_GPIO is now equivalent to GPIOLIB and features that depended on
GENERIC_GPIO can now depend on GPIOLIB to allow removal of this option.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Selecting CONFIG_DMADEVICES is optional, and we must
be able to continue even without DMA. Otherwise things
like omap4430sdp nfsroot will fail if DMA is not
selected.
Note that the driver already supports PIO mode, but
we fail to fall back to PIO if requesting DMA channels
fails.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
The spi-s3c64xx uses a Samsung proprietary interface for
talking to the DMA engine, which does not work with
multiplatform kernels.
This version of the patch leaves the old code in place,
behind an #ifdef. This can be removed in the future,
after the s3c64xx platform start supporting the regular
dmaengine interface. An earlier version of this patch was
tested successfully on exynos5250 by Padma Venkat.
The conversion was rather mechanical, since the samsung
interface is just a shallow wrapper around the dmaengine
interface.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
spi_bitbang_setup() deasserts the chip select line to initialise
the device. The chip select GPIO line is obtained from
spi_gpio->cs_gpios[] private data.
Currently, devices that are not registered under devicetree
environment will call into spi_bitbang_setup() with stale
cs_gpios[].
This patch ensures spi_gpio->cs_gpios[] is always initialised prior
to calling spi_bitbang_setup().
Reviewed-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Josef Ahmad <josef.ahmad@intel.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
There is no need to disable transmitter/receiver after each loop
iteration and re-enable it for next loop iteration. Enable the
transmitter/receiver before xfer loop starts and disable it when
the whole transfer is done.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Currently the driver only uses one internal chip select.
Add support for gpio chip selects configured by cs-gpios
DT binding.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
speed_hz is a write only member, so we can safely remove it and its
generation. Also fixes the missing clk_put after getting the periph
clock.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Dan Sneddon
Tarun Gupta
Ian Maund
Sana Venkat Raju
Alok Chauhan
Linux Build Service Account
Gabor Juhos
Geert Uytterhoeven
Daniel Santos
Jonas Gorski
Martin Schwidefsky
Michael Bohan
Jeff Hugo
Gilad Avidov
Kiran Gunda
Sagar Dharia
Stepan Moskovchenko
Kenneth Heitke
Harini Jayaraman
David Brown
Christian Eggers
Mark Brown
Mika Westerberg
Sylwester Nawrocki
Kuninori Morimoto
Peter Crosthwaite
Wei Yongjun
Lars-Peter Clausen
Linus Torvalds
Wolfram Sang
Mark Brown
Arnd Bergmann
Richard Genoud
Nicolas Ferre
Olof Johansson
Manjunathappa, Prakash
Thomas Abraham
Alexandre Courbot
Tony Lindgren
Josef Ahmad
Anatolij Gustschin