Rohit Vaswani 15c8581540 edac: cortex_arm64: Poll to check for cache errors ... By design, the CortexA53/A57 processors are incapable of gernerating interrupts or PMU events once a single-bit error is observed in the L2 caches. Hence, we need to poll the L2MERRSR register to periodically check for single bit errors. We need to do this for L2 on both clusters. Change-Id: I76a440b820f23c9667a5596cf550ff7725ec1cf5 Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>		2014-10-09 16:18:18 -07:00
..
amd64_edac.c	bitops: Introduce a more generic BITMASK macro	2014-09-03 20:02:49 -07:00
amd64_edac.h	bitops: Introduce a more generic BITMASK macro	2014-09-03 20:02:49 -07:00
amd64_edac_dbg.c
amd64_edac_inj.c
amd76x_edac.c
amd8111_edac.c
amd8111_edac.h
amd8131_edac.c
amd8131_edac.h
cell_edac.c
cortex_arm64_edac.c	edac: cortex_arm64: Poll to check for cache errors	2014-10-09 16:18:18 -07:00
cpc925_edac.c
e7xxx_edac.c
e752x_edac.c
edac_core.h	edac: Allow the option of creating a deferrable work for polling	2014-10-03 14:43:45 -07:00
edac_device.c	edac: device: Use poll_msec from registered edac device instead of default	2014-10-03 14:43:46 -07:00
edac_device_sysfs.c
edac_mc.c
edac_mc_sysfs.c
edac_module.c
edac_module.h
edac_pci.c
edac_pci_sysfs.c
edac_stub.c
ghes_edac.c
highbank_l2_edac.c
highbank_mc_edac.c
i7core_edac.c
i3000_edac.c
i3200_edac.c
i5000_edac.c
i5100_edac.c
i5400_edac.c
i7300_edac.c
i82443bxgx_edac.c
i82860_edac.c
i82875p_edac.c
i82975x_edac.c
Kconfig	EDAC: arm64: Add option to panic on correctable errors	2014-06-16 19:03:31 -07:00
Makefile
mce_amd.c
mce_amd.h
mce_amd_inj.c
mpc85xx_edac.c
mpc85xx_edac.h
mv64x60_edac.c
mv64x60_edac.h
octeon_edac-l2c.c
octeon_edac-lmc.c
octeon_edac-pc.c
octeon_edac-pci.c
pasemi_edac.c
ppc4xx_edac.c
ppc4xx_edac.h
r82600_edac.c
sb_edac.c	bitops: Introduce a more generic BITMASK macro	2014-09-03 20:02:49 -07:00
tile_edac.c
x38_edac.c