Debug symbols in installed kernel modules consume space
in the target filesystem, so strip them. Modules with
debug symbols should be present in the KERNEL_OBJ
location for debug purposes.
(cherry picked from commit bb77a75767f5dbb7327ab05f4ec4462b6ad62b10)
CRs-fixed: 400053
Signed-off-by: Nagender Telkar <ntelkar@codeaurora.org>
Change-Id: I4353e3733455e01cbe97c023d36b9bd3b7b8adf2
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
- AFE does not support sampling rate 44.1k
- This fix addresses the issue by setting backend proxy device
sampling rate to 48k
(cherry picked from commit 69ab7356a72981032d5d403ec1508dcfaeb7075f)
CRs-fixed: 413871
Signed-off-by: Jayasena Sangaraboina <jsanga@codeaurora.org>
Change-Id: Ic067178f9d4cdb51b8fee5292b960922088c8539
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
Currently, RMNET will restart the TX queue after receiving a
low-watermark notification from SMUX. This just clears the XOFF bit,
but does not reschedule the TX thread in the Linux TCP/IP stack. This
means that the next TX operation will not take place until the thread is
scheduled by some other means which may take up to 5 seconds.
Instead, wake the queue which clears the XOFF bit and schedules the TX
thread to allow transmission to continue immediately.
(cherry picked from commit 4d8fb2ecb3a9cdab3e9d605280256c6b46773dd0)
CRs-Fixed: 412758
Signed-off-by: Eric Holmberg <eholmber@codeaurora.org>
Change-Id: I1f169547f3ff518baada632d5a3f766b5795c697
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
The min_dpb required for smooth streaming is set for the
max requirement of 1080p playback session. This is set in
vidc platform data in the device file.
(cherry picked from commit 885fcc57354cd309f5ed0356da486d1e130b9ad7)
CRs-fixed: 408738
Signed-off-by: Mohan Kumar Gubbihalli Lachma Naik <mgubbi@codeaurora.org>
Change-Id: I38c3c9931f573cb029871bd48fd161f2158e139e
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
During playback of audio on earpiece path, the PA on the path
is the last component to be turned on. The turn on of PA can
cause a glitch in the output signal because the level of the PA
is not yet settled. Waiting for 20 msec after turning on the PA
avoids this glitch.
CRs-fixed: 417031
Signed-off-by: Bhalchandra Gajare <gajare@codeaurora.org>
(cherry picked from commit 1fa994d4aa256a536523f116232c4822b3495400)
Change-Id: Iaa7a47526c71d8b037df3d09cf30ede296c21356
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
In one corner case, the SD card is stuck in a bad state with its DAT0
line pulled low, and SDCC is waiting on the interrupt when the line
goes back high. But due its bad state eventually the SD card is removed
from the system.
Later during re-scanning of the devices, the SD card is power-cycled and
added to the system. But now the pending interrupts for SD card is
received as the interrupt MASK register (MCI_MASK0) was not cleared.
To prevent such cases reset the interrupt MASK register (MCI_MASK0) while
powering off to prevent any pending interrupts after power-cycle.
(cherry picked from commit a3f8f793b21782c79a9fcc5f7aa1cc27fcbf246e)
CRs-Fixed: 396706
Signed-off-by: Pratibhasagar V <pratibha@codeaurora.org>
Change-Id: Idfae18895abf47769328b0a768f83eba2ef573f7
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
Setting DDR timing mode in controller before setting the clock
rate will make sure that card don't see the double clock rate
even for very small amount duration. Some eMMC cards seems to lock
up if they see clock frequency > 52MHz.
(cherry picked from commit 2877d919135791d5223a9ba94b2cfc9ba50bc3df)
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Change-Id: I7a4ace461e2def6d53863db4b768ec7e497b3095
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
In the usb_ma_table there exist two consecutive values
that have IUSB_FINE_RES bit set. Some functions
incorrectly assume that this does not happen.
Fix this by checking for consecutive values having
IUSB_FINE_IRES bit set.
(cherry picked from commit 67ebde08e12d246302d133b4510d59c8f96325d1)
CRs-Fixed: 404348
Signed-off-by: David Keitel <dkeitel@codeaurora.org>
Change-Id: I6b6ca96b92ec4b9765e4812352057a0ac8cff380
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
Add msm_spm_get_vdd() API to return the core active voltage
Signed-off-by: Praveen Chidambaram <pchidamb@codeaurora.org>
(cherry picked from commit 4133ba1e1c9384910cd6db56130b654af115651d)
Change-Id: I76bcfbcb0eefda09757e9db86ba4adb76a44f2f7
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
This workaround can be removed in favor of an alternate solution
implemented in the power-collapse path which backs up the
corruptable L2CPUCPMR and L2CPMR registers before L2 power-collase
and restores them afterwards.
CRs-Fixed: 400700
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
(cherry picked from commit aa48fc35e051363b997bd33928796e3e84d08d88)
Signed-off-by: Ram Kumar Chakravarthy Chebathini <rcheba@codeaurora.org>
Change-Id: I4a9962d95a4a7a835042dde91eee6b89754ea86b
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
During power collapse, the AVSCSR register is always enabled and never
restored. This could result in AVS getting enabled on resume, when the
core is running at a frequency that doesn't support AVS.
Add new API, avs_enable, which restores the AVSCSR register based on the
saved AVSCSR register. Update the avs_disable API, to return the
AVSCSR register value prior to disabling the AVS.
(cherry picked from commit ad138da17fe08d46412d56b84309c5d17f7d5931)
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
Change-Id: I2bd2e1d6aea058e0f44c474da6c3121654f1236e
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
Currently, hash (SHA1/256/hmac) operation occasionally results
in an incorrect hash value. This is due to the premature reading
of the AUTH_IV register done before the last SHA block is processed.
There needs to be enough delay (wait states) before the AUTH_IV
register is read to extract the hash value.
The current implementation has 2 wait states. Adding 2 more wait states
for hash operations, resolves the issue.
The wait states are calculated based on the inputs from the hardware
team with regards to the time taken to process the last block of 16
bytes of the data packet.
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Change-Id: I82936441429560e41f25a98994d49a0113eb8de2
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
- During aac playback, multiple seek lead to target freeze.
- DSP starts decoding when internal buffer size maximum is
reached, hence, if there are corrupted frames in that buffer,
the entire set will not be decoded. This results in target freeze.
- Fix is to set the end of frame flag in the buffers that
are sent to DSP for decoding.
(cherry picked from commit 08508ac42fed7b1e3a7a9b7e098dfb4ceff8b836)
Signed-off-by: Swaminathan Sathappan <Swami@codeaurora.org>
Change-Id: Ic34272222dcb1df42d7e2fe5d028d513b8cf452f
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
LPASS clock are enabled out of reset on these SoCs, with PXO selected
as their undivided source. Because PXO rates are not present in the
frequency tables however, these clocks fail to handoff with reason
'HANDOFF_UNKNOWN_RATE'. As a result, clock_late_init() does not attempt
to disable these clocks in lateinit.
Add PXO rates to the LPASS frequency tables so that handoff succeeds
and, in lateinit, disables them if they are not used.
(cherry picked from commit ac15a37fd85089a2aef16624140a5d0a6cd1d71b)
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
Change-Id: Id8d674bfa3d41316be8aa14c5cc84baa77078d23
Signed-off-by: Neha Pandey <nehap@codeaurora.org>
The A330 GPU defines a few new registers that don't exist on
A305/A320. Define a new subset for A330 and dump it in the
postmortem and binary snapshot.
Change-Id: Ic0dedbadd0c44ee8872b99fd6b0b3dc8eb972eea
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
Expand the snapshot register dump helper function to support multiple
sets of registers. This will be useful for derivative GPUS that
use a global subset of registers and add a few new ones. This will
not be useful for chipsets that have extensive changes to existing
registers.
Change-Id: Ic0dedbad05bcc3b5a3a0cc933659959965ff5817
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
The CP MERCIU queue can be read from the A330 GPU. Dump it into
the snapshot binary.
Change-Id: Ic0dedbadf2c61ccec6a11af103374f4aee8be727
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
The A330 has a larger ROQ buffer then the A305/A320 variants so
adjust the size at runtime based on the core type.
Change-Id: Ic0dedbade62c988cfe402876bc94d91a2dd71617
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
Create adreno_is_a330() to identify the GPU for A330 specific
register settings and core specific code.
Change-Id: Ic0dedbade244ffba3ba3917661a88f97108e6182
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
Increase number of clocks that RBBM will wait before de-asserting
the Register Clock Active signal. This fixes kernel panics during
stability tests on multiple devices
Change-Id: I6f7f8bb17cfd9c5beed0fd21d56ab6ab9fd40195
Signed-off-by: Rammohan Basavaraju <rammoh@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
For A3xx, initialize UCHE_CACHE_MODE_CONTROL_REG to
0x00000001 so that UCHE will always use 64-byte
cachelines when we boot up or reset. This value
increases performance and was previously set in the
graphics preambles, but should instead be set at
boot/reset time.
Change-Id: Iec71ffc04262ac43534fd632d8b092a48d280509
Signed-off-by: Kevin Matlage <kmatlage@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
GPU register RB_GMEM_BASE_ADDR needs to be initialized with GMEM base
address. From A330, OCMEM is utilized to be GMEM dynamically; when
OCMEM is allocated for GFX, the allocated region address may vary
every time, GPU register RB_GMEM_BASE_ADDR need to be initialized
with the allocated OCMEM region address.
Change-Id: I5cb4472a9f18759d2af160a15d83f1404378a530
Signed-off-by: liu zhong <zhongl@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
No need to save a context if it is being destroyed since
it will no longer be used at all. This is better for
performance and also avoids the use of legacy kgsl
context save code for contexts that use preambles
Change-Id: I19a64e82188b4132f353bb61c21e4ed2281092fc
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
Define the register offsets for IOMMU-v2 and switch off using per
process pagetables for IOMMU-v2.
Change-Id: I8b76de557c8e52b5a2a333ceb987bd743b213eb7
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
Changed values written to VBIF registers for A330.
The maximum pending request from clients is increased to 24.
Disable VBIF clock gating. This potentially increases stand-by power.
Change-Id: Ic9a4f15546f4122298e140e79e4572c82e6385fc
Signed-off-by: Lokesh Batra <lbatra@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
Define the IOMMU register offsets in a structure array. This
offers flexibility in defining IOMMU v2 offsets in another array
and the right array to be used can be setup during MMU
initialization.
Also, restrict the usage of IOMMU offsets only in the iommu file
by redifining the functions that return iommu information. Remove
the function to get iommu mapped register address and replace
it with a function that returns the gpuaddress of given iommu
register. Only return the valid address bits of an iommu pagetable
instead of just returning the pagetable base register value.
Change-Id: Ib88e605f57e551c7b84029647451cb20f06025a0
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
Calling clk_set_rate() for both AXI & 2D core clocks without putting
them in async mode causes 2D core hang. Since AXI & 2D core clocks
are in sync mode, ensure that clk_set_rate() is called only for AXI
& 2D core clock is enabled only after it is prepared.
Change-Id: I4634e2342d62ce16ad7afc748b10b0573fbfd913
CRs-fixed: 385393
Signed-off-by: Ranjhith Kalisamy <ranjhith@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
Turn io_fraction to 100 so that the kernel
wait_io_interruptible call is not required for io_busy
reporting while using msm policy. Msm policy uses its
own schema to capture busy events.
Change-Id: Iddb63552305974ce4a12446117f27d07b7201387
Signed-off-by: Suman Tatiraju <sumant@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
Turn on an additional clock for IOMMU if it is valid. This additional
clock is present on devices which have the IOMMU unit access tied to
the core clock of another component. This has been introduced from
IOMMU-v2 onwards.
Change-Id: I8b0a0f23cb789d820a8d515cae54b44f556e634d
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
Set the upper limit for the gpu address that the MMU can access to
be the base address where the first IOMMU units register space
is mapped. Earlier we set it to the last address mapped minus
a PAGE_SIZE, but we can actually set it to the base address of the
first mapped unit since the GPU should never access that space
unless we are updating IOMMU registers.
Change-Id: I6507ee373a9218210c148685e443e948a311bd29
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
Limit the size of individual GPU memory allocations to the amount of
free memory on the system minus 32MB. This early check gives us the
chance to verify that the user didn't ask for an obscene amount of
memory, and also to limit the chance that an allocation attempt will
invoke the OOM killer.
The 32MB buffer in particular should keep us out of the clutches of
the OOM killer. That number is the same amount of buffer used in
the page allocation alogrithms and it should keep the GPU from further
throwing fuel on the fire of a low memory situation.
Change-Id: Ic0dedbadcc5ee9cc0d77056b1a22eed5c385d636
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
Instead of calling BUG_ON if the user passes a zero length via
IOCTL_KGSL_GPUMEM_ALLOC to kgsl_sharedmem_alloc_user, return
-EINVAL instead and propegate the error back up to the user.
CRs-fixed: 389886
Change-Id: Ic0dedbad2dc1f68ad1d3227498893c73c2a1c59e
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
If a platform has Trustzone support, enable GPU DCVS
automatically without checking the individual soc info
value.
Change-Id: Ie8d965f8d73283a7f3bf55dedc44d550db2408b8
Signed-off-by: Lucille Sylvester <lsylvest@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
Add a new sysfs node to communicate available GPU clock frequencies
to userspace for the power daemons.
Change-Id: I2479217aa797e2066cc50476ef7f73c5cae8aebe
Signed-off-by: Anshuman Dani <adani@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
Limit the number of pending requests from clients to just 1 for
better stability. More agressive values can be set later if things
are found to be stable.
Switch off gating next write request for certain clients, this
setting seems to be stable and should be better for performance
Set the register values for interleaving requests for A330 VBIF.
Do not set VBIF_OUT_AXI_AMEMTYPE_CONF0 since it was
only being set to POR value.
Change-Id: I2152a30b49545fdbf0c147106a088b71ed562e3f
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
Signed-off-by: Harsh Vardhan Dwivedi <hdwivedi@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
ion_import_dma_buf() can return a NULL without an error code. Detect
this condition & return a -EINVAL as error.
Change-Id: I18d058fd374a8d00c00bb943f496f446c9f1c90d
Signed-off-by: Ranjhith Kalisamy <ranjhith@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
Ensure that pagetable is updated during context destruction. This
resolves stability issues during Camera launch/exit scenarios. Applies
only to A20x GPUs. This change is already done for Z180 device.
Change-Id: I978cbce49ed2b45be0209c2939b1b8423c68d5ec
CRs-fixed: 381875
Signed-off-by: Ranjhith Kalisamy <ranjhith@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
it seems even if gpu requests for power rail off, modem might not
process this request as it leads to turn off power rail for mdp in
the case of 7x27a/8x25. This issue specific to 7x27a, since we do
soft reset the GPU on sleep/wake. In the case of suspend/resume,
the powerail is effectively off across the device.
Change-Id: Iad898da67b34e265b2447013c4250ba04a59c0cd
Signed-off-by: Rammohan Basavaraju <rammoh@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
Upon receiving the notification of an HDMI cable connection,
turn on HDMI core only if the default video resolution is
supported by the sink. Otherwise, HDMI core would be turned
on at a later time when it is configured with a supported
resolution by the userspace.
CRs-Fixed: 412575
Change-Id: I67cfb09bafa39646839877a66cd94f193c127a76
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
HDMI switch device is used to notify userspace components of the
availabilty of a connected HDMI sink. These notification should
only be sent whenever HDMI cable is connected or disconnected.
This patch removes all the redundant notifications.
CRs-Fixed: 412575
Change-Id: Ia5e60690a87569fce5d61a9af75d446648443e9b
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Add support for audio switch node in the HDMI driver that would
be used to notify audio userspace components of the availability
of an HDMI device.
CRs-Fixed: 412575
Change-Id: Idc41caf234810db52af9fcc89d2ed4ecbcaafc3b
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
HDMI core should not be powered down until the audio engine has
shutdown transmitting packets to the HDMI core. This change
increases the time for which the driver waits for the audio
engine to turn off.
CRs-Fixed: 412575
Change-Id: Ie11ab6c8140f7289f74da4877c9acf9b8cd4a838
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
DTV device should not be powered down until the audio engine has
shutdown. This change moves dtv audio off sequence to a separate
thread so that framebuffer close system call does not get blocked.
CRs-Fixed: 412575
Change-Id: I246a9e58f1367e653913773696510f375abf3d3a
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Implement Hot Plug Detect (HPD) software debouncing by
disabling the HPD interrupt until we finish processing
a previous HPD interrupt.
CRs-Fixed: 412575
Change-Id: Ia2c83f3446d09fe5bf6c6a1c4e6a9eb54ff465d6
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
For HDMI as primary case, we need to blackout the pipes
when they are unset so that any residue is not visible
on the DTV during suspend.
Change-Id: I2bf36f1002dd185c26fe6c4291977737daa73ae1
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
While changing the audio sampling rate, the older data in
the control register needs to cleaned before writing in
new data to avoid mixed or wrong data writing.
CRs-Fixed: 405772
Change-Id: I95d0807ea8cf544e4a0c8caed00de6cd60352efa
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Remove the kernel config parameter for HDCP since enabling or
disabling HDCP will now be controlled using a corresponding
module parameter.
Change-Id: Iae23b8fa66ca75d99423547e77f850f3c86615ee
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
This change removes the need to use HDCP feature flags in the
HDMI driver and adds the necessary support to configure HDCP
feature based on a module parameter.
Change-Id: Ie0eacc5b447230927cfdedfcb979c22d60e81981
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
This change adds a module parameter that can be used
to disable HDCP at runtime by specifying hdmi_msm.hdcp=0
on the fastboot command line.
Change-Id: Ifad5da9fcb86fb4ed663a5ef2bb14fe4dafd241e
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Currently, HPD(Hot Plug Detection, a module used for detecting
HDMI cable connection) soft debouncing logic implements around
1 sec mechanism to stabilize HPD event detection. In case of
fast HPD connect/disconnect, it is missing a real HPD event.
This change implements a new debouncing logic in driver which
will make sure the first real HPD event is correctly processed
and at the end of debouncing processing, if there is a change
in HPD state, the changed state is also processed. This way we
always process the change of HPD states.
CRs-Fixed: 384513
Change-Id: I02d9814e4a55b7eec11a8e0d134c9ed9b5747422
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
