Use the new license header with The Linux Foundation instead of CAF.
Change-Id: I73afbaf73ba47a7adf2b45f7f2c02fde330d2344
Signed-off-by: Willie Ruan <wruan@codeaurora.org>
Remove the parameter checks in pm_gpio_get and pm_gpio_set
callbacks because they are not necessary as callbacks of gpiolib.
This also removes an issue of NULL pointer check is after being
dereferenced.
Change-Id: Iaca83877fe93ba6335d40c9a36465f909aef2c97
Signed-off-by: Willie Ruan <wruan@codeaurora.org>
In revision 1 of the gpio block, the GPIO_STATUS1 GPIO_OK changes
from bit 1 to bit 7. Update the code to reflect this.
Also verify that PMIC pins have valid types and subtypes upon
probe. This allows us to make assumptions about correctness later
on when checking for capabilities of a pin in question.
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
(cherry picked from commit bfe64c7551275d24cb8eb45ff0b578427d68c2e0)
Change-Id: Idc7464799ff354b83c82e38004aa299356551630
Signed-off-by: Sudhir Sharma <sudsha@codeaurora.org>
If a gpio interrupt is already enabled, do not re-enable it again and do not
clear the interrupt status.
Before this patch: if an edge interrupt is marked as wakeup, the gpio sys
suspend will enable it. On resume, the gpio sys resume would clear the
intr_status of the wakeup irq. Thus, if this particular wakeup irq triggered
and woke us up, we would lose its intr_status before calling the gpio summary
handler. Now, when the summary handler is finally called, the irq handler for
the wakeup interrupt is never called.
With this change: we are *not* re-enabling the gpio-irq again to make sure that
when the irq framework unmasks all irqs on resume, it does not clear the
intr_status.
Change-Id: Ia5a9c6b00173a56b1abbdd4d4821becb7311d7f6
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Signed-off-by: Ajay Dudani <adudani@codeaurora.org>
Signed-off-by: Iliyan Malchev <malchev@google.com>
When gpios are set to input, we return the input buffer status
from the STATUS1 register when the 'get' gpiochip callback is
invoked. This register also includes a bit that indicates whether
the pin is enabled.
Check to verify the pin is enabled, and if it is then return the
properly masked 1-bit value. Otherwise return an error, since the
API is not valid in this state.
Change-Id: I715e17f076d0dbd67397812f98e308f863c59b7c
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
-fix address value updates when writing to register blocks
greater than 8 bytes.
-fix an invalid shift value being passed in for the 'invert' parameter.
-fix invalid use of MODE_CTL macros
-cleanup the control register read / write routines to
remove unused parameters.
Change-Id: I42223f30a8c6490370d9a8006ee13e028fe774e6
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
According to the TLMM_v3 hardware spec the INTR_POL_CTL bit
is to be set:
Low for level low interrupts;
High for level high interrupts;
High for all edge interrupts.
Make sure the software configures it as desired.
Change-Id: I3369def7bd00e427c7dfe109bcdd4b6e207ad239
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
The reset state for the INTR_CFG register is 0xE2. We need
the upper nibble to specify the target processor for the
gpio interrupt (Value 0x4 for APPS). But we were ORing
0x4 with 0xE still keeps it as 0xE. Get rid of the
incorrect read, modify, write cycle. Make sure the
reset state is wiped off before setting the interrupt
configuration bits.
Change-Id: I3deee9fcebe9eec78f89635313c5f3d0923fede5
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
The subtypes defined in the documentation have changed again.
Update both GPIO and MPP subtype values in the qpnp-pin driver to
reflect this.
Change-Id: I22e22414a74d724259706c927582d1573dc58875
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
GPIOs has only three modes where as MPP has seven. Change the
constraint check to check for the appropriate value based on the
pin type.
Change-Id: I53c85b4a5e852ef3b9d5dbe939a496053fa26197
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
Print the reason why a parameter constraint check failed to
improve debug capability.
Change-Id: Icd4a6457592bb4a73df61431dfcff63358bd7064
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
With TLMM-V3, the GPIO_INTR_STATUS register now requires
us to write 0 to clear the interrupt status. Earlier TLMM
versions required us to write 1 to clear the interrupt status.
Change-Id: Ic96ab6f3850fd4ac1164761c8f71c88e57fd4de5
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
The documentation followed to enumerate the subtype values was
found to differ from the actual implementation in hardware.
Update to the values actually found in the hardware.
Change-Id: I3a6d3027593bfb043b87d9c072c882981c649a6e
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
The gpio driver was not a true platform driver and hence wasn't
supported by device tree. This patch fixes that for non-DT targets
by making sure the device gets added early on during board init.
For DT-targets, adding the gpio-controller property for the device
makes sure the msmgpio device gets probed.
This change is done for all TLMM_v2 targets (msm8660 and future)
TLMM_V1 targets remain unaffected.
Change-Id: I8a55ab1e2af0366b3e6893b334ba2396d2a83190
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
After the change to keep the RAW_STATUS_EN always on, the
interrupt status bit was latched and could be set during
other (non-interrupt) activity on the GPIO line. This would
end up triggering the interrupt as soon as it was unmasked.
Hence, clear the interrupt status before unmasking the gpio
interrupt. This keeps the behavior and expectations same as
when the RAW_STATUS_EN was toggled and it prevented the
interrupt status to be updated while the interrupt was masked.
Change-Id: I3ccb31b5d8a7efe93f8253d4aff4a1c44281163f
CRs-Fixed: 346861
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Move enabling the RAW_STATUS_EN at the very beginning.
Hardware team clarified that it is better to write to
RAW_STATUS_EN before writing to any other INTR_CFG bits
in order to prevent spurious interrupts.
Removing writing to the GPIO_INTR_CFG_SU register for
gpio-v2 and remove modifying any other bits except
INTR_ENABLE in mask/unmask calls as it could cause spurious
interrupts as well.
Change-Id: Ia025b324ee3be8073960eac73899f733336cac4c
CRs-Fixed: 346861
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
The current code sets up irq attributes at postcore_init. But
with irqdomains, irqs are mapped later at runtime. Thus we need
to set these parameters within the irqdomain map routine for
systems that are using Device Tree.
Change-Id: I185ebc4efdb194d690ecbec75171709bd09e0588
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
TLMM v3 version has dedicated pads for only SDC1
and SDC2 among all SDC slots as opposed to v2 version.
Change-Id: I73c54f0a2799e6ffca74e5b846ac8339d0af3bb8
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
The official name for copper is MSM8974.
Switch to it.
Change-Id: Ifb241232111139912477bf7b5f2e9cf5d38d0f9e
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
Add mpp support to the qpnp-pin driver. MPP support allows for
additional devices to be specified in the Device Tree topology.
This support is implemented in the same driver as the GPIO
support since the address map is very close between them.
The addition of this support does not change the existing gpio
support.
Default MPP configuration can be specified in the Device Tree
using the three new bindings for mpp. Any attribute not specified
in the Device Tree will assume its default configuration.
It's also possible to configure an MPP at runtime using the
existing qpnp_pin_config() API. If a given configuration feature
is not supported by the underlying hardware pin, then that
particular request is silently dropped with no error. This allows
for gpio users to continue specifying only a subset of the full
qpnp_pin_cfg structure.
Change-Id: I2b72768647de2a371edfa05c52fc1ed776c215c0
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
There are two types of failures given a config parameter and a
requested value. The first type occurs due to a requested
configuration not being supported by the harware. The second case
happens when there is ample hardware support, but the
configuration value requested is out of spec.
Change the behavior so that a failure due to a lack of hardware
support does *not* trigger an error in either the probe of
default pin configuration, or the qpnp_pin_config() API.
The main motivation here is so that the pin configuration can be
extended to support mpp in addition to gpio. Users should be able
to only specify parameters for configuration items they care
about. For example, it would not be reasonable for a gpio pin to
receive configuration specification for mpp parameters. Given
that there's only one data structure in this scenario, this
cannot allow the config request to fail.
This change also has the added benefit of restructuring the code
so that there is no duplicated checks for the same error
conditions in the driver.
Change-Id: I88776b304b25cf4bb0a49ff305b398209aaade2a
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
qpnp-gpio manages gpio_chip queries based on the slave
ID. This has a limitation in that it restricts the number of
gpio_chips per slave ID to one. However, some PMICs have both MPP
and GPIO on the same slave, and thus the slave ID is not a
meaningful unit to search for.
Instead, make use of the 'label' binding to give the
primary dev-container node a name. This name will serve as the
gpio_chip label, which can be used in lookups.
Change-Id: Ic20caeb4622d73449a983992275446c733ddd89a
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
Since QPNP PMICs also include support for MPP, and since we
intend to support MPPs in the same code base, it's not
appropriate to limit this the scope of this driver to 'gpio'.
Change the driver name to 'pin' since it more accurately
describes the potential for this driver.
Also update the Device Tree include files for the name changes.
Remove a superflous 'gpio-pin' definition in the msmcopper
specific include file, since such configuration shall never
change. This binding should be defined in the PMIC specific
include only.
Change-Id: Id1d6407039908e3cf44dfc19af71f0cdc7aff8e6
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
Pointers are more flexible than index numbers, since index
numbers depend upon an additional reference to the array in
question. In particular, we'd like to add a new API to lookup a
devnode based on a predefined name in the Device Tree. This API
will return a spmi_resource, and so it's natural to want to use
this pointer directly with the other existing APIs.
Also introduce a new API spmi_for_each_devnode that can be used
to iterate each spmi_resource in the dev_node array. This
abstracts the traversal of the array, which was previously done
within the existing APIs.
Change-Id: I18f9397e5d78770e840a9f95dd8061201931df6e
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
It turns out that the only use cases for the qpnp library use
the existing spmi data structures. As such, there's really
no justification for having the library not be called 'spmi'.
There is nothing Qualcomm specific about this code.
Also cleanup some inconsistencies in the Kernel Doc comments
while we're here.
Change-Id: I1c73c88be740b6f5d38ba2de62de1737981b30fa
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
The following merge commit chose the irq_domain implementation
from AU_LINUX_ANDROID_ICS.04.00.04.00.126 instead of the version
in v3.4.
commit f132c6cf77251e011e1dad0ec88c0b1fda16d5aa
Merge: 23016de 3f6240f
Author: Steve Muckle <smuckle@codeaurora.org>
Date: Wed Jun 6 18:30:57 2012 -0700
Merge commit 'AU_LINUX_ANDROID_ICS.04.00.04.00.126' into
msm-3.4
Since this version is inconsistent with the upstream,
port the irq_domain framework to the version in v3.4 and
makes all necessary changes to clients that are out of spec.
Details of client ports are below.
-Update the qpnp-int driver for revmap irq_domain API. The revmap
irq_domain implementation introduces a reverse lookup scheme using
a radix tree. This scheme is useful for controllers like qpnp-int
that require a large range of hwirqs.
-Bring the ARM GIC driver up to v3.4, being careful
to port existing CAF changes.
-Partially port the gpio-msm-common driver to the new irq_domain API.
Enable the gpio-msm-common driver to work with the new irq_domain
API using a linear revmap. It is not a full port since irq_domain
is still only registered for Device Tree configurations. It should
be registered even for legacy configurations.
In addition, the irq_domains .map function should be setting all
the fields currently done in msm_gpio_probe(). That's not
currently possible since msm_gpio_probe is invoked
unconditionally - even from Device Tree configurations.
Finally, gpio-msm-common should be converted into a real
platform_device so that probe() is invoked due to driver and
device matching.
Change-Id: I19fa50171bd244759fb6076e3cddc70896d8727b
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
To unmask a gpio interrupt, the gpio driver sets the
INTR_RAW_STATUS_EN and INTR_ENABLE bits in the INTR_CFG register.
As soon as the INTR_RAW_STATUS_EN is set, the INTR_STATUS is updated
and this causes a spurious interrupt when the irq is enabled.
This is noticed frequently when the gpio is pulled high and requests
a rising edge interrupt or pulled low and is requesting a falling edge
interrupt.
Due the internal circuit design of the TLMM IRQ block, the above method
causes a spurious interrupt when the irq was initialized.
Hence, to avoid this behavior we set the INTR_RAW_STATUS_EN, clear the
INTR_STATUS only once during setup. Every mask and unmask only toggles
the INTR_ENABLE bit.
CRs-Fixed: 346861
Change-Id: I1c9852ed91432582c3d050ccf933053fd368b216
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Update the gpio_xlate callback due to prototype changes
introduced by this change:
commit 15c9a0acc3
Author: Grant Likely <grant.likely@secretlab.ca>
Date: Mon Dec 12 09:25:57 2011 -0700
of: create of_phandle_args to simplify return of phandle
parsing data
Change-Id: I9d6aa57d32388aa21c1a621bf49a7f78769ae06d
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
Add a gpio_chip driver to support the Qualcomm SPMI PMIC
architecture called QPNP. The driver supports Device Tree
and allows a device_node to be registered as a gpio-controller.
The driver also specifies APIs to allow a non-Device Tree user
the ability to configure the PMIC GPIOs.
This driver does not handle interrupts for GPIOs directly.
Instead, that work is handled by the existing qpnp-int driver.
This is feasible since the interrupt register map for all
QPNP peripherals is the same.
Change-Id: I04eb39d9855b0957f0647010fcb203ec2fc83c7c
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
In the process we replace the upstream versions of the file with
our own and introduce gpio-msm-v3.c and gpio-msm-common.c.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add support for multi-purpose pins (MPPs) on Qualcomm PM8xxx
PMIC chips.
PM8xxx MPPs can be configured as digital or analog inputs or
outputs, current sinks, or buffers.
Note that mpp pins appear as gpio lines to the kernel. However they
are implemented separately from the pmic's gpio driver as
mpps have different configuration attributes and have different
register controls than the pmic's gpio controller. Basically they are
different set of pins.
Change-Id: Iab39b2f7c2ba3f35ef6ac74d37ee7add8c70681f
Signed-off-by: David Collins <collinsd@codeaurora.org>
Add support for GPIO on Qualcomm PM8xxx PMIC chips.
Change-Id: I5c00baeedc6c40ed40065d15c83577051e6ac9c6
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Fixes the following compiler warnings:
drivers/gpio/gpio-samsung.c: In function ‘samsung_gpiolib_init’:
drivers/gpio/gpio-samsung.c:2980:1: warning: label ‘err_ioremap1’ defined but not used [-Wunused-label]
drivers/gpio/gpio-samsung.c:2978:1: warning: label ‘err_ioremap2’ defined but not used [-Wunused-label]
drivers/gpio/gpio-samsung.c:2976:1: warning: label ‘err_ioremap3’ defined but not used [-Wunused-label]
drivers/gpio/gpio-samsung.c:2974:1: warning: label ‘err_ioremap4’ defined but not used [-Wunused-label]
drivers/gpio/gpio-samsung.c:2722:55: warning: unused variable ‘gpio_base4’ [-Wunused-variable]
drivers/gpio/gpio-samsung.c:455:32: warning: ‘exynos_gpio_cfg’ defined but not used [-Wunused-variable]
drivers/gpio/gpio-samsung.c:2126:33: warning: ‘exynos4_gpios_1’ defined but not used [-Wunused-variable]
drivers/gpio/gpio-samsung.c:2228:33: warning: ‘exynos4_gpios_2’ defined but not used [-Wunused-variable]
drivers/gpio/gpio-samsung.c:2373:33: warning: ‘exynos4_gpios_3’ defined but not used [-Wunused-variable]
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Jean-Francois Dagenais reported:
Configuring a gpio pin with the gpio-pch driver with
"IRQF_TRIGGER_LOW | IRQF_ONESHOT" generates an interrupt storm for
threaded ISR until the ISR thread actually gets to physically clear
the interrupt on the triggering chip!! The immediate observable
symptom is the high CPU usage for my ISR thread task and the
interrupt count in /proc/interrupts incrementing radically.
The driver is wrong in several ways:
1) Using handle_simple_irq() does not provide proper flow control
handling. In the case of oneshot threaded handlers for the
demultiplexed interrupts this results in an interrupt storm because
the simple handler does not deal with masking/unmasking. Even
without threaded oneshot handlers an interrupt storm for level type
interrupts can easily be triggered when the interrupt is disabled
and the interrupt line is activated from the device.
2) Acknowlegding the demultiplexed interrupt before calling the
handler is wrong for level type interrupts.
3) The set_type function unconditionally enables the interrupt. It's
supposed to set the type and nothing else. The unmasking is done by
the core code.
Move the acknowledge code into a separate function and add it to the
demux irqchip callbacks.
Remove the unconditional enabling from the set_type() callback and set
the proper flow handlers depending on the selected type (level/edge).
Reported-and-tested-by: Jean-Francois Dagenais <jeff.dagenais@gmail.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Initialization of irqenable, irqstatus registers is the common
operation done in this function for all OMAP platforms, viz. OMAP1,
OMAP2+. The latter _gpio_rmw()'s which supposedly got introduced
wrongly to take care of OMAP2+ platforms were overwriting initially
programmed OMAP1 value breaking functionality on OMAP1.
Somehow incorrect assumption was made that each _gpio_rmw()'s were
mutually exclusive. On close observation it is found that the first
_gpio_rmw() which is supposedly done to take care of OMAP1 platform
is generic enough and takes care of OMAP2+ platform as well.
Therefore remove the latter _gpio_rmw() to irqenable as they are
redundant now.
Writing to ctrl and debounce_en registers for OMAP2+ platforms are
modified to match the original(pre-cleanup) code where the registers
are initialized with 0. In the cleanup series since we are using
_gpio_rmw(reg, 0, 1), instead of __raw_writel(), we are just reading
and writing the same values to ctrl and debounce_en. This is not an
issue for debounce_en register because it has 0x0 as the default value.
But in the case of ctrl register the default value is 0x2 (GATINGRATIO
= 0x1) so that we end up writing 0x2 instead of intended 0 value.
Therefore changing back to __raw_writel() as this is sufficient for
this case besides simpler to understand.
Also, change irqstatus initalization logic that avoids comparison
with bool, besides making it fit in a single line.
Cc: stable@vger.kernel.org
Cc: Tony Lindgren <tony@atomide.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Grant Likely <grant.likely@secretlab.ca>
Reported-by: Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
Tested-by: Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
In 3.3, gpio wakeup setting was broken. The call
enable_irq_wake() didn't set up the PXA gpio registers
(PWER, ...) anymore.
Fix it at least for pxa27x. The driver doesn't seem to be
used in pxa25x (weird ...), and the fix doesn't extend to
pxa3xx and pxa95x (which don't have a gpio_set_wake()
available).
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Fixes the following warning when "SAMSUNG EXYNOS5" is not selected:
warning: ‘exynos5_gpios_1’ defined but not used [-Wunused-variable]
warning: ‘exynos5_gpios_2’ defined but not used [-Wunused-variable]
warning: ‘exynos5_gpios_3’ defined but not used [-Wunused-variable]
warning: ‘exynos5_gpios_4’ defined but not used [-Wunused-variable]
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
The variable 'bit' is uninitialized in the first iteration of for
loop. Fix it.
Signed-off-by: Axel Lin <axel.lin@gmail.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
The irqdomain api changed significantly in v3.4 which caused a build
failure for this driver.
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Acked-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Cc: Hans J. Koch <hjk@linutronix.de>
Cc: Torben Hohn <torbenh@linutronix.de>
When Tegra30 support was added to the Tegra GPIO driver, a few places
which iterated over all banks were not converted to use the variable
tegra_gpio_bank_count rather than hard-coding the bank count. Fix this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Olof Johansson <olof@lixom.net>
Tegra20 and Tegra30 share the same register layout within registers, but
the addresses of the registers is a little different. Fix the driver to
cope with this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Olof Johansson <olof@lixom.net>
Pull more ARM updates from Russell King.
This got a fair number of conflicts with the <asm/system.h> split, but
also with some other sparse-irq and header file include cleanups. They
all looked pretty trivial, though.
* 'for-linus' of git://git.linaro.org/people/rmk/linux-arm: (59 commits)
ARM: fix Kconfig warning for HAVE_BPF_JIT
ARM: 7361/1: provide XIP_VIRT_ADDR for no-MMU builds
ARM: 7349/1: integrator: convert to sparse irqs
ARM: 7259/3: net: JIT compiler for packet filters
ARM: 7334/1: add jump label support
ARM: 7333/2: jump label: detect %c support for ARM
ARM: 7338/1: add support for early console output via semihosting
ARM: use set_current_blocked() and block_sigmask()
ARM: exec: remove redundant set_fs(USER_DS)
ARM: 7332/1: extract out code patch function from kprobes
ARM: 7331/1: extract out insn generation code from ftrace
ARM: 7330/1: ftrace: use canonical Thumb-2 wide instruction format
ARM: 7351/1: ftrace: remove useless memory checks
ARM: 7316/1: kexec: EOI active and mask all interrupts in kexec crash path
ARM: Versatile Express: add NO_IOPORT
ARM: get rid of asm/irq.h in asm/prom.h
ARM: 7319/1: Print debug info for SIGBUS in user faults
ARM: 7318/1: gic: refactor irq_start assignment
ARM: 7317/1: irq: avoid NULL check in for_each_irq_desc loop
ARM: 7315/1: perf: add support for the Cortex-A7 PMU
...
Primarily gpio device driver changes with some minor side effects
under arch/arm and arch/x86. Also includes a few core changes such as
explicitly supporting (electrical) open source and open drain outputs
and some help for parsing gpio devicetree properties.
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Merge tag 'gpio-for-linus' of git://git.secretlab.ca/git/linux-2.6
Pull GPIO changes for v3.4 from Grant Likely:
"Primarily gpio device driver changes with some minor side effects
under arch/arm and arch/x86. Also includes a few core changes such as
explicitly supporting (electrical) open source and open drain outputs
and some help for parsing gpio devicetree properties."
Fix up context conflict due to Laxman Dewangan adding sleep control for
the tps65910 driver separately for gpio's and regulators.
* tag 'gpio-for-linus' of git://git.secretlab.ca/git/linux-2.6: (34 commits)
gpio/ep93xx: Remove unused inline function and useless pr_err message
gpio/sodaville: Mark broken due to core irqdomain migration
gpio/omap: fix redundant decoding of gpio offset
gpio/omap: fix incorrect update to context.irqenable1
gpio/omap: fix incorrect context restore logic in omap_gpio_runtime_*
gpio/omap: fix missing dataout context save in _set_gpio_dataout_reg
gpio/omap: fix _set_gpio_irqenable implementation
gpio/omap: fix trigger type to unsigned
gpio/omap: fix wakeup_en register update in _set_gpio_wakeup()
gpio: tegra: tegra_gpio_config shouldn't be __init
gpio/davinci: fix enabling unbanked GPIO IRQs
gpio/davinci: fix oops on unbanked gpio irq request
gpio/omap: Fix section warning for omap_mpuio_alloc_gc()
ARM: tegra: export tegra_gpio_{en,dis}able
gpio/gpio-stmpe: Fix the value returned by _get_value routine
Documentation/gpio.txt: Explain expected pinctrl interaction
GPIO: LPC32xx: Add output reading to GPO P3
GPIO: LPC32xx: Fix missing bit selection mask
gpio/omap: fix wakeups on level-triggered GPIOs
gpio/omap: Fix IRQ handling for SPARSE_IRQ
...
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Merge tag 'mfd_3.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-2.6
Pull MFD changes from Samuel Ortiz:
- 4 new drivers: Freescale i.MX on-chip Anatop, Ricoh's RC5T583 and
TI's TPS65090 and TPS65217.
- New variants support (8420, 8520 ab9540), cleanups and bug fixes for
the abx500 and db8500 ST-E chipsets.
- Some minor fixes and update for the wm8994 from Mark.
- The beginning of a long term TWL cleanup effort coming from the TI
folks.
- Various fixes and cleanups for the s5m, TPS659xx, pm860x, and MAX8997
drivers.
Fix up trivial conflicts due to duplicate patches and header file
cleanups (<linux/device.h> removal etc).
* tag 'mfd_3.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-2.6: (97 commits)
gpio/twl: Add DT support to gpio-twl4030 driver
gpio/twl: Allocate irq_desc dynamically for SPARSE_IRQ support
mfd: Detach twl6040 from the pmic mfd driver
mfd: Replace twl-* pr_ macros by the dev_ equivalent and do various cleanups
mfd: Micro-optimization on twl4030 IRQ handler
mfd: Make twl4030 SIH SPARSE_IRQ capable
mfd: Move twl-core IRQ allocation into twl[4030|6030]-irq files
mfd: Remove references already defineid in header file from twl-core
mfd: Remove unneeded header from twl-core
mfd: Make twl-core not depend on pdata->irq_base/end
ARM: OMAP2+: board-omap4-*: Do not use anymore TWL6030_IRQ_BASE in board files
mfd: Return twl6030_mmc_card_detect IRQ for board setup
Revert "mfd: Add platform data for MAX8997 haptic driver"
mfd: Add support for TPS65090
mfd: Add some da9052-i2c section annotations
mfd: Build rtc5t583 only if I2C config is selected to y.
mfd: Add anatop mfd driver
mfd: Fix compilation error in tps65910.h
mfd: Add 8420 variant to db8500-prcmu
mfd: Add 8520 PRCMU variant to db8500-prcmu
...
This branch contains a handful of driver updates, mostly to
the LPC32xx platform but also for Samsung EXYNOS and Davinci.
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Merge tag 'drivers2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull "ARM: More SoC driver updates" from Olof Johansson:
"This branch contains a handful of driver updates, mostly to the
LPC32xx platform but also for Samsung EXYNOS and Davinci.
It had a few context conflicts against patches already merged through
fixes-non-critical. We should have resolved this early during the
development cycle by pulling them in as a dependency, instead I did it
after the fact this time."
* tag 'drivers2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
gpio/samsung: use ioremap() for EXYNOS4 GPIOlib
gpio/samsung: add support GPIOlib for EXYNOS5250
ARM: EXYNOS: add support GPIO for EXYNOS5250
ARM: LPC32xx: Ethernet support
ARM: LPC32xx: USB Support
ARM: davinci: dm644x evm: add support for VPBE display
ARM: davinci: dm644x: add support for v4l2 video display
ARM: EXYNOS: Hook up JPEG PD to generic PD infrastructure
ARM: EXYNOS: Hook up G2D PD to generic PD infrastructure
arm: lpc32xx: phy3250: add rtc & touch device
ARM: LPC32xx: clock.c: Clock registration fixes
ARM: LPC32xx: clock.c: jiffies wrapping
ARM: LPC32xx: clock.c: Missing header file
ARM: LPC32XX: Remove broken non-static declaration
ARM: LPC32xx: clock.c: Fix mutex lock issues
ARM: LPC32xx: clock.c: warning fix
ARM: LPC32xx: Added lpc32xx_defconfig
Pull ARM platform updates from Russell King:
"This covers platform stuff for platforms I have a direct interest in
(iow, I have the hardware). Essentially:
- as we no longer support any other Acorn platforms other than RiscPC
anymore, we can collect all that code into mach-rpc.
- convert Acorn expansion card stuff to use IRQ allocation functions,
and get rid of NO_IRQ from there.
- cleanups to the ebsa110 platform to move some private stuff out of
its header files.
- large amount of SA11x0 updates:
- conversion of private DMA implementation to DMA engine support
(this actually gives us greater flexibility in drivers over the old
API.)
- re-worked ucb1x00 updates - convert to genirq, remove sa11x0
dependencies, fix various minor issues
- move platform specific sa11x0 framebuffer data into platform files
in arch/arm instead of keeping this in the driver itself
- update sa11x0 IrDA driver for DMA engine, and allow it to use DMA
for SIR transmissions as well as FIR
- rework sa1111 support for genirq, and irq allocation
- fix sa1111 IRQ support so it works again
- use sparse IRQ support
After this, I have one more pull request remaining from my current
set, which I think is going to be the most problematical as it
generates 8 conflicts."
Fixed up the trivial conflict in arch/arm/mach-rpc/Makefile as per
Russell.
* 'platforms' of git://git.linaro.org/people/rmk/linux-arm: (125 commits)
ARM: 7343/1: sa11x0: convert to sparse IRQ
ARM: 7342/2: sa1100: prepare for sparse irq conversion
ARM: 7341/1: input: prepare jornada720 keyboard and ts for sa11x0 sparse irq
ARM: 7340/1: rtc: sa1100: include mach/irqs.h instead of asm/irq.h
ARM: sa11x0: remove unused DMA controller definitions
ARM: sa11x0: remove old SoC private DMA driver
USB: sa1111: add hcd .reset method
USB: sa1111: add OHCI shutdown methods
USB: sa1111: reorganize ohci-sa1111.c
USB: sa1111: get rid of nasty printk(KERN_DEBUG "%s: ...", __FILE__)
USB: sa1111: sparse and checkpatch cleanups
ARM: sa11x0: don't static map sa1111
ARM: sa1111: use dev_err() rather than printk()
ARM: sa1111: cleanup sub-device registration and unregistration
ARM: sa1111: only setup DMA for DMA capable devices
ARM: sa1111: register sa1111 devices with dmabounce in bus notifier
ARM: sa1111: move USB interface register definitions to ohci-sa1111.c
ARM: sa1111: move PCMCIA interface register definitions to sa1111_generic.c
ARM: sa1111: move PS/2 interface register definitions to sa1111p2.c
ARM: sa1111: delete unused physical GPIO register definitions
...
