size + strlen("qcom-") is equal to the length of string not including the
null character. However, we are comparing it to the length of the buffer,
so we need to include the null character, and make a change to make sure
(size + strlen("qcom-")) is smaller than CRYPTO_MAX_ALG_NAME.
Change-Id: I882e2c3e761a4bd4344ce8820b26cf890f29bab3
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Expose APIs to enable qcrypto client to select any specific qcrypto
instance.
Change-Id: Ia96f7fa0f15216c0656aa6dc495db350b3c574a8
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Moves bus scaling code to architecture independant directory
for platform drivers.
Change-Id: Ie0d5b104882d1534fae262af85e99cc09a56ab04
Signed-off-by: Dan Sneddon <dsneddon@codeaurora.org>
During driver algorithm registration, if there are errors, the
dynamically allocated memory needs to be free on the error return.
Otherwise, there will be memory leak. This patch fixes memory leak
accordingly.
Change-Id: Ic3c65ebd3d6c7b0e88815e6750ec14990e375587
Acked-by: Chemin Hsieh <cheminh@qti.qualcomm.com>
Signed-off-by: Niranjana Vishwanathapura <nvishwan@codeaurora.org>
This patch enables rfc4309(ccm(aes)) algorithm. Further more, it fixes
an issues with ccm. According to RFC3610, associate
data is optional. The assocaite data length can be 0 as shown in
testmgr ccm rfc4309 test vectors. The driver did not take this zero
length of associate data situation into account. And the corresponding
test vectors in testmgr may fail.
Change-Id: I2f269a54ad269a8ba72c0e570a7859da223e2d9b
Acked-by: Chemin Hsieh <cheminh@qti.qualcomm.com>
Signed-off-by: Niranjana Vishwanathapura <nvishwan@codeaurora.org>
Remove the sps header file from older location as sps
driver and clients need to use new header file from
new location include/linux.
Resolve the warnings/errors from client drivers due to
new sps header changes.
Change-Id: I1cdb87756abf3425a9bb5d8bf89cd1aa03a01716
Signed-off-by: Dipen Parmar <dipenp@codeaurora.org>
Upstream prefers existing drivers be converted to support multiplatform
kernels. This requires drivers to be located in directories that
contain generic functionality instead of specific mach directories.
Move the socinfo driver into drivers/soc/qcom and update the initcall
levels to satisfy dependencies.
Change-Id: If195cd793d84867d371f25136a88f2a7ce239500
Signed-off-by: Xiaocheng Li <lix@codeaurora.org>
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
If ce clock is not disabled in suspend state, memory may be corrupted
and device can not wake up. We add an optional flag "clk_mgmt_sus_res"
for qcrypto driver. This flag indicates if the ce clocks need to be
disabled in suspend function and enabled in resume function of qcrypto
driver. When the flag is set, we disable the clocks that are not disabled
in suspend function and re-enable them again in resume function.
Change-Id: I23be38b2765c0cc5f3ed41d65f8e4ae8a9372d18
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Architectural changes in the ARM Linux kernel tree mandate
the eventual removal of the mach-* directories. Move the
scm driver to drivers/soc/qcom and the scm header to
include/soc/qcom to support that removal.
Change-Id: Ie660d0566de35045c1ba73fcddeda99efacf057e
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
Add optional crypto algorithm flags to indicates if to use SW crypto
algorithms instead of HW algorithms. Based on it, we then rename and
register crypto algorithms to be qualcomm specific to prevent clashing
with the default SW implementation of the algorithms used by dm_crypt
module. (used for disk encryption).
Change-Id: I39badf22581791c502a247f8f37123f513b8c77e
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
The break is missing in the switch-case branch of writing xts du size,
this leads to incorrect xts du size setting.
Change-Id: I288c3d30cc3d59eb28672be32aa57819971ca97f
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Hardcoding key length to a constant value results in overwriting
command element information in the command descriptor beyond what
is allocate for the key information in the command element list.
This results in corruption of the command list in the case where
command descriptors are used for configuring crypto registers and
needlessly writing to key registers that are not relevant to the
operation (when writing to registers directly), and thus leads to
crypto operation failures. Fix is to use the key length based on
what is requested by the client.
Change-Id: Ibd625dc7a438fac84b13588700bf472004e246d5
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
This reverts commit 8d175c9d77, which
release pbam memory when an error occurs. However, on a device with
multiple ce, pbam memory is shared by multiple pce_dev, it can only
be freed when the reference count goes to zero, and can not be
released it if reference count is not zero when an error occurs.
The previous implementation on bam_release was correct, so we
revert commit 8d175c9d77.
Change-Id: Ibc3b83dd46ea087c7a0084d032d96a2848f6baf5
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Add support for holding system from suspending while an operation
is in progress (when clks are enabled). This is done by invoking
pm_stay_awake before enabling clks (when a crypto operation is
initiated) and invoking pm_relax when crypto operation is done.
Change-Id: I5c7ceb025f6cac1b7c985fc1c308e82f851fca72
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Architecutural changes in the ARM Linux kernel tree mandate the
eventual removal of the mach-* directories. Move the
mach/clk-provider and mach/clk header to include/linux/clk.
Change-Id: I495f8332bf5d0d09ccfb236c819dea2bacb13542
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
We no longer support MSM9625 so remove various files and code associated
with it. This is not a complete removal of MSM9625, but just removing
dts files, any file with 9625 in name, and any code that was associated
with CONFIG_ARCH_MSM9625.
Change-Id: I3d5405bb71a529806797adc81dd628996000acdc
Signed-off-by: Kumar Gala <galak@codeaurora.org>
This change removes source files from the kernel tree that
were not being used during make. The list of used files
was generated using an annotated make log and was then
compared with new files added since the public release of
kernel version 3.10.00. New files which were added but
not used have been removed from the tree.
A diff was also run to determine the list of files that had
been modified since the release of kernel version 3.10.00.
These files were then scrubbed based on the current kernel
configuration, removing invalid and unused conditionals.
Some files which support planned functionality or are
useful in debugging have been excluded from this reap.
Change-Id: Ia44a224d3cea7bc78dd45e8a8279860d35d4b008
Signed-off-by: Ian Maund <imaund@codeaurora.org>
This patch provides support of multiple variable size packet
API to the ota_crypto driver.
Furthermore, this patch replaces snprintf with scnprintf
to make pointer manipulation save when display stats.
Change-Id: I56aebd24557dccc547ff86cb8853ace0602b6e50
Acked-by: Chemin Hsieh <cheminh@qti.qualcomm.com>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
select qce50 for APQ8084 architecture and then bring up crypto driver
on APO8084
Change-Id: I4235dbf88003203353c7d8b18093136bef1b62d1
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
change physical address type to support LPAE for crypro drivers on
APQ8084
Change-Id: I2a85c5db9d131c3be469a5f6b322bc3c4a317400
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Release pmab memory when an error occurs as well.
Change-Id: I7aa13d5a03edbdfa806345039459feaeac6e7a11
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
snprintf can return more than the size of buffer, which is not
expected here, obviously. Use scnprintf instead.
Change-Id: I3b97a016df910728dfef5a0914ab8ad67c68e39c
Signed-off-by: AnilKumar Chimata <anilc@codeaurora.org>
According to the specification of AEAD, AEAD request cryptlen is
not a Fixed maximum and assoclen is also same. This could lead to
potential integer overflow, thus allocating less memory. So we
need to check potential integer overflow on AEAD request length.
Change-Id: I58a0c5e1a6e890bad30f7865e96b7db46337158c
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
This patch fixes two issues. One issue is to do with simultaneous requests
of a ahash tfm. The other issue is to do with ahash import, and export
functions.
Agent issues chain of requests in sequence of init, followed
by multiple updates, and final to the crypto driver for the hashing of a
buffer. Each request can be asynchrounous. After a request is complete,
the next one in the sequence is issued.
Multiple simultaneous async requests can be issued to the driver
for the same tfm if they are for independent hashing.
In the driver, the state variables such as trailing buffer, first
block, last block are maintained in the driver. The
state variables are maintained in the request context, instead of
tfm context. Otherwise, simultaneous async requests can
confuse each other. This patch moves those variables out of
tfm context to request context to fix this issue.
Agent above the driver can import/export ahash state of a request. This
patch fixes a few issues in the driver to support import/export.
First issue, the byte count returned from hw for hmac has 64 bytes of
padding on the first request to the hardware. In the import/export this
special case needs to be accomodated.
The 2nd issue is the state buffer is only updated after hardware operation
complete. For the first, data being accumulated in the trailing buffer,
and if request has not ever issued to the hw, when import function comes,
the trailing data needs to be exported. This patch uses trailing
buffer directly as state buffer variable for import and export.
The context update functions after hareware request complete are not
necessary and they are removed. The last issue is to do with state
variable count. It was not initialized. That may cause hashing generated
wrong digest after export and import.
Change-Id: I608c2322b120825b9ca12c3794e0b0a4628ef693
Acked-by: Chemin Hsieh <cheminh@qti.qualcomm.com>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
hmac-sha1 and hamc-sha256 have variable mac key up to a block size.
If user provides a key that is less than the block size, the
key should be padded with zero to the block size before it is
given to the hw.
This padding was not done properly in the driver.
When switch engine between ahash hmac(sha1), hmac(sha256),
and ipsec, problem may happen. ipsec takes 20 bytes of key.
The generated digested data is wrong, even though everything looks
fine from driver. ipsec may fail.
Furthermore, this patch cleanup the driver to do proper setup of
hardware to use hw key or pipe key.
Change-Id: I128eca5a1ac4df326ea1ca9aef2bf27323c1c82f
Acked-by: Chemin Hsieh <cheminh@qti.qualcomm.com>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Fixes null pointer exception in count scatter gather function. Scatter
gather list pointer become NULL if the sg pointer reaches last but one
node, which results in NULL pointer exception.
Change-Id: I634baf30074e6e53ffa22635565da54e9ae43150
Signed-off-by: AnilKumar Chimata <anilc@codeaurora.org>
Fix buffer overflow for a non-zero byteoffset value.
Also fixes memory leak issue by adding data_len check in check_params.
One of the scenarios data_len can be less than byteoffset which results
in memory leak with huge data length, which might cause the kernel panic.
Change-Id: I3f773673219f45dad4f17499b1ee0feda2aff1f7
Signed-off-by: AnilKumar Chimata <anilc@codeaurora.org>
Unsigned int variable is compared for < 0, which is an invalid if
condition. This patch removes the check.
Change-Id: I76c10223672db2c387e025697dd8bd921e5ddc1b
Signed-off-by: AnilKumar Chimata <anilc@codeaurora.org>
Kasumi/snow-3g f8/f9 are defined by 3gpp, as the algorithms for
UMTS, and LTE for over the air ciphering and integrity. The
algorithms are supported by crypto 5 hardware. This patch
enables qce50 driver to provide Kasumi/snow-3g f8/f9
ciphering and integrity services.
Change-Id: I7b157e7f178cbe869dcb686a417ac8a5cd4a648a
Acked-by: hemin Hsieh <cheminh@qti.qualcomm.com>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Validate that the sha_ctx is initialized before any SHA operation
(update, final) requests is issued by client.
Change-Id: I83ac2000d860dfef5532910a2a73cd927b68e95f
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Verify sum of all data segments equals the total data length.
Change-Id: I0fb9d856281d52c58536e77512f8cae75544d1bc
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Check to confirm the sum of length of the source
and destination segments is equal to the total length
sent by client.
Change-Id: Ib10b8f792591631060135022d81f1f08c424ee66
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Use VERIFY_WRITE to check write access to destination buffers
before writing to them.
Change-Id: If9708695e85659bb25e13762c54dd50abd9577c7
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
This patch provides support for multiple qcrypto devices
with the qcrypto driver.
Change-Id: I36b0a802dcf92a438353f5961fab0bfddc53268a
Acked-by: Chemin Hsieh <cheminh@qti.qualcomm.com>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
In the situation of more than one requests, the ce clock may get
errorneously disabled even when there are active requests. The
scaling operation is then modified to fix the problem and ensure
all requests are completed when disable the clock. We also clean
up the related codes.
Change-Id: Icc4675fa7b3818f6f8befb513b56d9ae051b98de
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Based on the context flags set by client, set XTS_DU_SIZE
register to sector size of 1KB, or the actual total length
of the packet.
Change-Id: Id461a27013f99301c3ca9e714f397f33c3f6ba03
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Due to uninitialized "flags" field in the request structure,
incorrect choices are made in the qce driver layer with
regards to setting crypto hardware registers.
Initializing the flags fixes this incorrect setting of the
registers.
Change-Id: Ic40319ea5e15e66cbafd28f727a9bcc6ea41b1ca
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
In some platforms such as fsm9900, multiple instances of qce50 hw
may be supported. Each qce50 HW has an ndp-bam. Each qce50 HW
can support multiple instances of qce_dev platform device.
Each qce_dev has its own configured pipe set and associated qce50 HW,
defined by crypto-base and bam-pipe-pair fields in the device tree files.
This patch based on io address, it decides to create a new qce50 hw
instance or use the existing known instance at device probe time.
Furthermore, this patch does iomap for only once for each HW BAM instance
to avoid issue with bam driver. If modprobe, and rmmod of qcedev,
and qcrypto are not in first in last out order, kernel may crash in
bam driver in the last rmmod.
This saves virtual space for IO if multiple instances of qcedev
share the same instance of HW BAM.
Change-Id: I1565b1976981b0512832ff793e0adb29c4be3ccc
Acked-by: Chemin Hsieh <cheminh@qti.qualcomm.com>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Encryption processing at qcrypto driver includes three main steps:
set ce high bandwidth and enable ce clock in cra_init, then send
encrytion request, and at last set ce low bandwidth and disable
clock in cra_exit. This process is fine for the use case where
there are lots of requests between cra_init and cra_exit, but will
introduce large overhead for mmc layer disk encryption as it calls
cra_init, queue request and cra_exit for every encryption request.
It is not necessary to set low bandwidth and disable clock for every
encrypt request when it is completed. So we delay these scaling down
tasks for a while, and just scale down the last request when timer
expires so as to amortize and decrease the overhead.
Change-Id: I6a59066343f01950b66f4e886d40a9f27ce211c3
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
The only version that needs verifiation is major version to ensure
HW CE 5.0 is being used. Minor and step versions checks are not
needed to gate driver loading.
Change-Id: I2052f511f3f2286da78a9c8d4ccf9803fbd6f204
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Fix -EBADMSG error for crypto 5.1 and above for aead decipher.
bam dma input/output length should include asso data plus iv plus crypto
data, and excluding MAC result for deciphering.
Change-Id: I0aaa666dbe96185cf0a81a542b3df02d4f6ebf88
Acked-by: Chemin Hsieh <cheminh@qti.qualcomm.com>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
CE HW sharing is not supported when BAM hardware is used, so
we need to set the corresponding ce_shared flag as zero in
qcedev_probe().
Change-Id: I28f0cb9c453a473970742f80fc16379ec7183771
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Memory was not assigned to ignore_buffer pointer and uninitialized
pointer was being used.
Change-Id: Ie7c372aeafdfe17b9bb70d38666fa81c3df1e043
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
When client sets HW_KEY flag, driver should ignore key data
and length when client issues set_key request.
When client sets PIPE_KEY flag, driver should ignore key data.
Change-Id: I550d1d2a217e6b9c9de50064bfafe72f9f32e6e1
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Currently there is no way of instructing the crypto driver
to use HW specific capabilities. The kernel crypto framework
does not expose any API to set any specific HW feature flags:
ex: use of HW key, use of PIPE keys, setting XTS data unit
size.
The driver currently uses a specific key pattern to decide
when to instruct HW to use HW_KEY (uses key pattern of all
zeros) and when to use PIPE_KEY (uses key pattern of all 0xF's).
This limits the use of the specific key pattern from ever being
used for any crypto operation.
Adding support for crypto client to set flags to indicate when
to use HW KEY, PIPE KEY, size removes the limitation on the key
patterns that can be used by the driver.
Adding XTS data unit size flags allows the client to take
advantage of the hardware capability to set data unit size
for XTS operations.
Change-Id: I0d1417a6d3c990e0750dbd90e3816f45fec8d693
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
There exist scenarios on some platforms where the same CE HW used in
crypto driver is shared with the crypto driver in secure execution
environment. In these case, crypto BAM is set to operate in master
mode by secure EE. Hence it needs to be registered to operate in
satellite mode by HLOS crypto driver.
Change-Id: Ibc5e06aac09c53dd6e1b419b871d9da3f82ab63d
Signed-off-by: Hariprasad Dhalinarasimha <hnamgund@codeaurora.org>
Add support_hw_key, hw_key flag to indicate if use of
HW KEY is supported by the driver.
Change-Id: If7976f5891afa211631597b8dab93ff17f0fa5c5
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
This patch provides multiple hw devices support for ota crypto driver.
The driver dynamically allocates hardware resources for each ota crypto
operations. Further more, the stat structure in the driver
is changed to support device tree.
Change-Id: I701fe08ecc51f53ddbe6e2b76b2fb65ab79190d2
Acked-by: Chemin Hsieh <cheminh@qti.qualcomm.com>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
CRYPTO clocks has to be enabled regardless of hardware sharing,
hence remove the hardware sharing check.
Change-Id: I551e8a97768e0526783a6ccfe9a214f1a9de148e
Signed-off-by: Hariprasad Dhalinarasimha <hnamgund@codeaurora.org>
When SPS driver reports a failure to process a request,
we need to output the sps_iovec_contents that was issued
to the SPS driver.
Change-Id: I84d48880cade41e5b9ce652f4dba1a84b857fb72
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
There is potential for HEAP corruption when the
byte offset field is set to a huge value.
Change-Id: Idd851cf3ec57627aba7d8250914cd18ccdd697ec
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
This patch handles the operation completion status
during the completion of a crypto operation properly.
The crypto device status register is clear at the beginning of
each operation.
Change-Id: I54e38160c939c17fe58ebdce44f8080b3837e3e7
Signed-off-by: Hariprasad Dhalinarasimha <hnamgund@codeaurora.org>
AES-CCM error does not report proper status to qcrypto driver.
If prior operation AES CCM operation has an error, (ex: MAC_FAILED),
it never gets cleared. Subsequent operation will report the same bit
error. Fix is to clear the status register before firing off an
operation
Further more, any AES-CCM error due to MAC failed is not logged
properly. Add aead_msg_fail if aead opearation is fine, but MAC
comparison fails the integrity checking.
Change-Id: Id9057a0f3fdf0be0b4e09185ae3a31d52ffd9c01
Signed-off-by: Hariprasad Dhalinarasimha <hnamgund@codeaurora.org>
For decrypt operation AUTH_POS bit is set incorrectly to 0x02
resulting in the authentication being done before decryption.
For decryption, the AUTH_POS field should be configured to 0x1
(or 0x3) to ensure authentication is occurring after decryption.
Change-Id: Ieaf10a653c6e77994c285e573d7fd787634631a2
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
On platform that use device tree to pass board or architecture
specific information rather than via platform device structure,
the id field of platform_device structure is no longer valid.
It was used to identify different instance of Crypto engine.
With device tree, this is set to -1.
The crypto driver modules (qcrypto and qcedev) refers to pdev->id
mostly to update statistics counters. With invalid pdev->id,
the counter does not increment, and would corrupt memory as it
update counters in _qcrypto_stat[-1] and _qcedev_stat[-1].
This patch removes all reference to pdev->id.
Change-Id: Ia8723c6eb5e91806223696efb1bf1a480ff2d831
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
replace sg_copy_to_buffer(), and sg_copy_from_buffer()
in crypto driver with version that uses scatterwalk_sg_next
to traverse the sg list.
After setting up an IPsec tunnel with DES-CBC encryption and HMAC-SHA1
authentication, following messages were displayed while running a few ping
packets.
[ 121.773780] bytes copied=0x8 bytes to copy= 0x58
[ 122.781008] bytes copied=0x8 bytes to copy= 0x58
[ 123.781113] bytes copied=0x8 bytes to copy= 0x58
[ 124.781175] bytes copied=0x8 bytes to copy= 0x58
This kind of messages are displayed when sg_copy_to_buffer() or
sg_copy_from_buffer() fail to copy entire data. They were able to
copy only part of it.
This happens because sg_copy_to_buffer() and sg_copy_from_buffer()
do not recognize scatter-buffer buffer used in Crypto. It needs to
use scatterwalk APIs to traverse the scatter-buffer list.
To address this issue, qcrypto_copy_from_buffer() and
qcrypto_copy_to_buffer() functions are newly added. These are similar
to sg_copy_to_buffer() and sg_copy_from_buffer(), but they understand
the scatter-gather list used in Linux crypto subsystem.
Change-Id: I71167e7e56aee8ddaa405f30a3f9f5dab426e6c8
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
CE clk needs to be enabled when invoking sps_exit. Further
more, memory allocated for pipe FIFOs should not be de-allocated
before calling sps_exit, as it is still referenced in sps_exit.
Change-Id: I66cbd7d92ed7ad74d5b4eca23fe3a327501b2e1b
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
There exists scenarios where packet processing is done in softirq
which runs in interrupt context. Blocking call is not allowed in
interrupt context. The qcrypto driver tries to allocate memory in
several places, and some of them were done in interrupt context.
In some cases, to meet the alignment requirement of some versions
of Crypto5 engine, _copy_source() is called that make a copy of
the data. This calls kmalloc() with GFP_KERNEL flag. This flag cannot
be used in interrupt context since the caller may get blocked until
the kernel finds requested memory.
To avoid this, all the memory allocation requests in interrupt context
were changed to use GFP_ATOMIC flag instead.
Change-Id: I3b86af00f3d7737c38b94e748ae083f58576dda5
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Mismatch of qce50 HW definitions in include file and SWI.
Change-Id: Ic5a01588841b8d245ac9fbea333d019b3ed1e937
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
The cause of the crash is due to uninitialized variable "areq" used in
ablk_cipher_req().
When the areq is pulled from pce_dev->areq, it is not valid and is
uninitialized. Since we already have the valid pointer to areq from
qce_req structure, we do not need to redefine areq.
Change-Id: Ib63ec65dc9df5f87ff470c04cfe5fbb66c19199a
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Add support to determine when to use command descriptor (CD)
based on register settings and set flag to indicate BAM
global device control is managed remotely. This configuration
is used when the device does not support accessing CE HW
registers using BAM command descriptors (HW registers are
not managed locally by BAM).
Change-Id: Ic3195db03ecc73e98b7dd3407ccc5402e703b362
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Use previously configured register setting instead of
determining what bits needs to be set per operation.
Change-Id: Ie22c0ce4dd5ca14b030ec8ad6feaaf511535b145
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Some chipsets that support CE 5.0 HW does not support
setting CE HW registers via BAM command element/descriptors.
These registers need to be set directly.
This patch adds support to configure CE HW registers directly
without using BAM consumer pipe.
Change-Id: I0707fcd5bf132c9462b8c6a30f6f7d8f8dd6fd86
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Remove registration of call back function and the call back
function for consumer pipe operation.
The callback does not do anything significant but
add to the latency per operation.
Change-Id: Id272a1311e2c3e2872091b599ac40f590fb9b0f7
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
There exist scenarios where memory gets corrupted due
to the limitation on the number of descriptors that
can fit into the PIPE descriptor FIFO.
The fix is to increase the max number of descriptor by
128 (to 0x500).
Change-Id: I770374043ad11cf320ca1bec1f00840b10b86218
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Add support for enabling clk before initiating crypto
operation and disabling clk after all crypto operations
are complete.
Expose qce_clk_enable() and qce_clk_disable() APIs for
qce clients (qcedev and qcrypto).
Add clk scaling and gating in the qcedev and qcrypto
driver modules.
Change-Id: I6ab96f6b62f2401bf721483448601d52af1be19e
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Check to ensure keylength is valid for HMAC operation.
Change-Id: I7f0075cad2dc1f011e32309b3e96641cfc4dcd9e
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
For AES-XTS 256 mode, key size is 64 bytes (twice the
AES key size of 32 bytes). The driver only checks for
AES key size and not specifically for xts key size.
The driver checks for AES key size and return a failure
for AES XTS 256 where key size is 64 bytes
Fix is to check for valid keys for XTS algorithm.
Change-Id: Ia7bafa5b5c13eab018a2e1d729a82c8d329a092e
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
When using PIPE keys, the XTS_DU_SIZE register is hardcoded to
512 Bytes. For transfers that are smaller than 512 bytes,
the crypto operation hangs waiting for more data.
The fix is to set XTS_DU_SIZE to minimum of packet size and 512
bytes.
Change-Id: I0dea9fadc71c599df700c1431f793e7cbb9997b0
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
When the number of entries in the scatter gather list is larger
than 64, crypto operation fail. This is due to incorrect use
of macro to allocate memory for the descriptor size.
Fix is to replace use of QCE_SIZE_BAM_DSCR with the size of the
sps_iovec data structure. Further, more use the correct macro when
reporting the size of the descriptor to BAM.
Change-Id: I4396ad8407b6b91d7a34367a2777cb920f81457b
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
ce-core_src clk is being left on preventing device from going
into low power mode. Furthere more, clks are enabled without
checking if the handle is valid.
This fix removes enabling of ce_crore_src_clk. Also checks if
clk handle is valid before enabling them.
Change-Id: Ieb64b4b11385838ba18dd05d47ccc978e5b1bdf1
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Add clk enable/disable and init/deinit APIs.
These APIs will be used in future to allow clk scaling and
gating by clients.
Change-Id: I08503972b9ed77633e14d81711aa92c61df7a0ad
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Based on the encryption key value, check if the request
requires using the PIPE keys. If so, set appropriate
configuration registers to indicate to HW to use PIPE keys.
Change-Id: I8ddf6c7b372dc63479e1bd105bbcb8c127ff1513
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Stress test case scenarios involving a cipher operation for a large
packet (> 32KB) followed by a hash operation (of any data packet size)
fails, with the hash operation hanging.
The failure is due to the sps driver invoking the incorrect callback
for the subsequent hash operation. Instead of invoking the registered
hash operation callback, it invokes the previously registered cipher
operation callback.
The fix is to set the correct flag bits for the event when registering
the callback before invoking sps_register_event() and also removing
the SPS_EOT_EVENT flag when registering the sps_connect pipe information.
Change-Id: Ia9ef774e2900df61f18298349fb4b5f4dc4d34b2
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Add the "shared" field in the ce_hw_support data structure.
This field indicates if the crypto HW used by the HLOS crypto
driver is being shared across multiple execution environment(s).
Change-Id: Ie8038c6bc7268dab2353f3a7f24b59d37aad2bb8
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Remove EOT flag set on the data descriptor issued on the producer
PIPE. As per the hardware documentation EOT flag does not need
to bet set for producer pipe descriptors.
Change-Id: Iec05ff6b7db1b9a1c94bc8a23f8ba8c9bc45b446
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Before starting any authentication operation we need to
ensure all encryption related configurations are invalid.
This is done by setting the encryption config register to 0.
Change-Id: I294834c78a46063bb3c564cdebcaafbc5f846952
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
PMEM functionality is deprecated.
Remove all references to CONFIG_ANDROID_PMEM.
Remove all pmem related functionalities.
Change-Id: I70e5e308e37d25f8b0e788dbad6617925e4331bd
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Treating scatter gather list as an array is and referencing
entries with indexes results in incorrect sg entries.
Tnis is because the sg entries are not contiguous in some
scenarios.
Fix is to use scatterwalk_sg_next() to traverse the sg list.
Change-Id: I1d7ebec779fa18c3ab5f0a6f357ef7fb53d3e9ab
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Fix the null pointer errors and valid index checking for arrays to
fix potential kernel crash.
Change-Id: Iabf7f73dcfe5a544e3fe83f1e67ec1161f989fac
Signed-off-by: Hariprasad Dhalinarasimha <hnamgund@codeaurora.org>
Using sg_virt() on scatter list entries, that is designated
for buffers in high memory pages, results in returning a 0
address; NULL pointer is returned. This is due to the fact
that high memory pages are by definition unmapped. Hence
sg_virt() does not work for such pages. Dereferencing this
NULL pointer to copy data from/to results in kernel panic.
Remove all cases of sg_virt() API use case.
Change-Id: I5a007f5d198dff8265f0247aa83adf04b9511f5d
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
There exists scenarios, where data is copied from client's
scatter gather list (sglist) to a locally allocated buffer.
In these cases, the driver uses sg_virt() API to retrieve
the virtual address of the buffer for each of the sglist
entry.
Using sg_virt() on scatter list entries, that is designated
for buffers in high memory pages, results in returning a 0
address; NULL pointer is returned. This is due to the fact
that high memory pages are by definition unmapped. Hence
sg_virt() does not work for such pages. Dereferencing this
NULL pointer to copy data from/to results in kernel panic.
Fix is to use sg_copy_from_buffer()/sg_copy_to_buffer() to
copy data between a local buffer and the buffer pointed to by
the sglist. These APIs temporarily maps the memory addresed
by each of the sglist entries using kmap() and copies data
from this mapped segments to the requested local buffer.
Change-Id: Ibaaf218f3f86a35c67368c7b2ee57189db207bca
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
sg_next() may find wrong scatter-gather buffer in crypto subsystem,
and this causes a kernel crash. scatterwalk_sg_next() should be used
instead in crypto related drivers.
Change-Id: Ia8b87a91165e915d3b0709331a83e3b40bd02493
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
The Current BAM descriptor FIFO is set to 512 bytes and
can accomodate 32 descriptor entries (each entry being 8 bytes
and pointing to a unique sg entry from the sg list). There
exists clienta that can issue a scatter gather list with
more than 32 entries.
Increasing the size to accomodate a max of 1024 entries
allows driver to process all clients request successfully.
Change-Id: Ide111de0ef001642543c503574b7f080185f9c8b
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
When performing a crypto operation of packet size larger
than 32KB -1 Bytes (max supported by BAM HW), the operation hangs.
The root casue was identified to be in one of the accumulators of
NDP_BAM not being given enough time to clear prior to when the EOT is
seen from the crypto core.
The workaround to the above issue in NDP_BAM is to precess the data
descriptors in in the producer PIPE in 2 steps.
- Enable INT for the second last descriptor prior to sending the last
results dump data descriptor to BAM
- Once the interrupt is fired, then only issue the result dump data
descriptor to be process by BAM
The above changes results in allowing enough time for the accumulators
to clear before the last results dump data descriptor is processed by
BAM.
Change-Id: I46be19857fc22bae7aec2b2798ca487ee49fafd1
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
sg_next() may find wrong scatter-gather buffer in crypto subsystem,
and this causes a kernel crash. scatterwalk_sg_next() should be used
instead in crypto related drivers.
Change-Id: Ibb454bc8a8b2c0318e55cd12ba3e4ca2f3647e36
Acked-by: Ho Lee <holee@qti.qualcomm.com>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
OEM specific HW key (primary hardware key) is XPU protected by
trustzone and is not accessible by HLOS.
Only the Qualcomm specific HW key (secondary key) is made
available to HLOS. This patch removes access to OEM specific HW
key and replaces with the QC HW KEY.
Change-Id: I7a22218c4673c57d385eaaa8d445a93e7bc300f6
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
When the crypto driver modules, qcedev and qcrypto are both
configured to be built-in (not loadable), one of the probe
call fails.
This is due to both of them trying to register the same
CE BAM device to sps driver: both invokes "sps_register_bam_device".
BAM devices need to be registered only once.
Fix is to use a flag to indicate if the BAM device is already
registered and maintain a bam_register count for the number of
request made for this registration.
Also since we dont need to initialize the bam_register count in
the init function, the module_init/module_exit are removed
Change-Id: I1ba9a0320f049d605b4aecf013a46997f5bccfda
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
When an error is encountered while trying to register a BAM
device, unlock the mutex before returning with an error.
Change-Id: I71fd8c3e69cee23406992ec61aeab0191d26fb71
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Currently, hash (SHA1/256/hmac) operation occasionally results
in an incorrect hash value. This is due to the premature reading
of the AUTH_IV register done before the last SHA block is processed.
There needs to be enough delay (wait states) before the AUTH_IV
register is read to extract the hash value.
The current implementation has 2 wait states. Adding 2 more wait states
for hash operations, resolves the issue.
The wait states are calculated based on the inputs from the hardware
team with regards to the time taken to process the last block of 16
bytes of the data packet.
Change-Id: I4f9e784fbfca62d6636d87dc44c1bf9992e3b3e4
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
AES-CCM mode is currently failing due to numerous issues.
Following fixes have been made to make AES CCM mode operations
pass:
- Initialize the hash commandlist
- Set LAST bit in ENCR_CFG register to indicate single operation
- Set AUTH_SEC_CFG register correctly for decryption
Change-Id: I15d1e48046246e9ca7441a6214869abfa9f62edf
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Remove dummy command elements added for the DES/DES3 CBC algorithm.
In order for proved perfromance, the descriptor (data and command)
size sent to the BAM needs to be multiple of burst size (set to 64B).
Change-Id: If9b0cef79f15da73b18d55c24c32f4c0b7b1216a
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
XTs mode of operation fails with a crash or hangs in some cases.
This failure is due to numerous reason:
- CRYPTO_XTS_DU_SIZE address is incorrect resulting
in not setting the register correctly
- xts_du_size command list pointer was NULL. This results in
the operation crashing due to dereferenciong of a NULL pointer
- XTS KEY register was not set correctly, resulting in
incorrect results for encrypt/decrypt operation
After fixing the above XTS mode of operation is passing.
Change-Id: I1cfcfaf0ecae61510d3d4372c49a412d65d7bc40
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
CTR mode operation fails due to incorrect CNTR IV returned
for large size packets. For large packets, adding the number
of crypto blocks (16 byte chunks) to the CNTR_IV3 register
sometimes results in oevrflowing the register and hence an
incorrect value is reported back.
The counter IV for CTR/XTS mode is calculated incorrectly.
Th fix is to account for roll over scenarios. when the updated
counter value exceeds 0xFFFFFFFF.
Change-Id: I9343c520ce17871145eb9678d5fed9d718ddc089
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Multiple back to back CBC packets encryption followed by
decryption operation is failing. This failure is due to
incorrect CNTR IV calculated at the end of the operation
that is used in the subsequent operation.
Fixed the value of the cntr iv for decryption mode.
The CNTR IV should point to the last 16 bytes of the
encrypted data packet.
Change-Id: Ibca400a3a34ab448e54508f4019410edaaca4977
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
HMAC operation for small and large packets are failing.
This is due to 2 reason:
- Packet size set for each operation is larger than what is
supported by the BAM hardware.
- Byte count value read after the end of the operation is of
incorrect byte order.
Fix is to decrease the max packet to the max of (32KB-64) and
fix byte order when storing the byte count value from the register
dump of the results at the end of the operation.
Change-Id: Ieb91ab2ad22cb8a08a575c058b7178e532bea7d7
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Add pipe locking logic. Before accessing the CE HW,
lock all other pipes from accessing the same CE HW.
After the operation is complete, unblock the pipes.
The pipe pairs should also belong to the same group.
Change-Id: Ie696ad0efcb4b38c1fd43b315d468067bb3b8a1a
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Currently the BAM's execution enviornment parameter is not set.
Without setting this parameter, there would be no interrupts handled
on HLOS.
Signed-off-by: Ramesh Masavarapu <rameshm@codeaurora.org>
Currently the AXI clock is not enabled for the crypto driver.
Without this clock enabled, data will not be transferred
between the DDR and the Crypto Engine.This fix enables the
AXI clock.
Signed-off-by: Ramesh Masavarapu <rameshm@codeaurora.org>
The Crypto Engine hardware does not generate an End of Transfer (EOT)
interrupt for SHA algorithms. This issue is solved by:
-Adding an INT flag for the last descriptor on the producer pipe.
Signed-off-by: Ramesh Masavarapu <rameshm@codeaurora.org>
The NWD flag had to be enabled only on the last data descriptor
and not in intermediate descriptors.
Signed-off-by: Ramesh Masavarapu <rameshm@codeaurora.org>
According to the hardware design, Crypto Engine 5.0
hardware expects all descriptors to be burst-size
aligned for performance reasons. In the case of using
descriptors, unaligned addresses have a huge performance
impact. In this case it might cause h/w to take longer
processing times when compared to the crypto driver directly
setting the registers via processor.
Signed-off-by: Ramesh Masavarapu <rameshm@codeaurora.org>
Crypto cipher/authentication operation yields incorrect results.
Although the operation is succesfull, the resulting data bytes
seems to be incorrect. The data input/outout needs to be
configured to be in little endian format.
The fix is to set the LITTLE ENDIAN flag in the CRYPTO_CONFIG
register, after configuring the crypto hardware registers and
prior to setting the GO_PROC register. This way, the little
endian format kicks in for the the data descriptor transfer
only, resulting in correct order in which bytes are input and
output.
Signed-off-by: Ramesh Masavarapu <rameshm@codeaurora.org>
Initialize the platform data before it is being used for bus scaling.
Change-Id: Ie41ddec08b52b44ae735469dd8f3052e3469eeff
Signed-off-by: Hariprasad Dhalinarasimha <hnamgund@codeaurora.org>
Add new register definitions for QCE5.0 Hardware
Add new HAL (qce50.c) for interfacing with CE 5.0 hardware:
-- Implement the new interface to BAM (instead of data mover).
-- Add support for multiple Pipes.
-- Add support for use of HW key.
Change-Id: I69dc3993f607553d4752f9f9fb4fdfe1a09a6345
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Incorrect HMAC values are generated in following scenarios.
- In case of a single transfer with a packet shorter than the
block size, the HMAC generated is incorrect. This is due to
the "FIRST" bit in AUTH_CFG register not being set. When calling
HMAC_final for a transfer with a single packet (with no prior HMAC
updates), the "FIRST" and "LAST" bit in AUTH_CFG register needs to
be set. Currently FIRST bit is being cleared incorrectly for all
scenarios.
- In a scenario of a mac key input larger than block size, the key
needs to be hashed. The key hashing operation is crashing. This is
due to a NULL, unintialized pointer to the device handle. This is
fixed by intializing the pointer correctly. Further more, key size
is uninitialized, resulting in corruption of buffer.
Change-Id: Iec736f2130e509fcaf631a2c71c5483514666617
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Add device tree support for qcedev and qcrypto device drivers.
Add documentations for associated bindings.
Change-Id: Ib76986af5d9e30263a559329acbca401ec3304d2
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Pull crypto fixes from Herbert Xu:
"This fixes a build problem in sahara and temporarily disables two new
optimisations because of performance regressions until a permanent fix
is ready"
* git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6:
crypto: sahara - fix building as module
crypto: blowfish - disable AVX2 implementation
crypto: twofish - disable AVX2 implementation
The sahara crypto driver has an incorrect MODULE_DEVICE_TABLE, which
prevents us from actually building this driver as a loadable module.
sahara_dt_ids is a of_device_id array, so we have to use
MODULE_DEVICE_TABLE(of, ...).
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Javier Martin <javier.martin@vista-silicon.com>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Pull crypto fixes from Herbert Xu:
"This push fixes a crash in the new sha256_ssse3 driver as well as a
DMA setup/teardown bug in caam"
* git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6:
crypto: sha256_ssse3 - fix stack corruption with SSSE3 and AVX implementations
crypto: caam - fix inconsistent assoc dma mapping direction
Fixes a race on driver init with registering algorithms where the
driver status flag wasn't being set before self testing started.
Added the cra_alignmask field for CBC and ECB modes.
Fixed a bug in GCM where AES block size was being used instead of
authsize.
Removed use of blkcipher_walk routines for scatterlist processing.
Corner cases in the code prevent us from processing an entire
scatterlist at a time and walking the buffers in block sized chunks
turns out to be unecessary anyway.
Fixed off-by-one error in saving off extra data in the sha code.
Fixed accounting error for number of bytes processed in the sha code.
Signed-off-by: Kent Yoder <key@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
req->assoc is dma mapped BIDIRECTIONAL and unmapped TO_DEVICE.
Since it is read-only for the device, use TO_DEVICE both for mapping
and unmapping.
Cc: <stable@vger.kernel.org> # 3.9, 3.8
Signed-off-by: Horia Geanta <horia.geanta@freescale.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Pull crypto update from Herbert Xu:
- XTS mode optimisation for twofish/cast6/camellia/aes on x86
- AVX2/x86_64 implementation for blowfish/twofish/serpent/camellia
- SSSE3/AVX/AVX2 optimisations for sha256/sha512
- Added driver for SAHARA2 crypto accelerator
- Fix for GMAC when used in non-IPsec secnarios
- Added generic CMAC implementation (including IPsec glue)
- IP update for crypto/atmel
- Support for more than one device in hwrng/timeriomem
- Added Broadcom BCM2835 RNG driver
- Misc fixes
* git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (59 commits)
crypto: caam - fix job ring cleanup code
crypto: camellia - add AVX2/AES-NI/x86_64 assembler implementation of camellia cipher
crypto: serpent - add AVX2/x86_64 assembler implementation of serpent cipher
crypto: twofish - add AVX2/x86_64 assembler implementation of twofish cipher
crypto: blowfish - add AVX2/x86_64 implementation of blowfish cipher
crypto: tcrypt - add async cipher speed tests for blowfish
crypto: testmgr - extend camellia test-vectors for camellia-aesni/avx2
crypto: aesni_intel - fix Kconfig problem with CRYPTO_GLUE_HELPER_X86
crypto: aesni_intel - add more optimized XTS mode for x86-64
crypto: x86/camellia-aesni-avx - add more optimized XTS code
crypto: cast6-avx: use new optimized XTS code
crypto: x86/twofish-avx - use optimized XTS code
crypto: x86 - add more optimized XTS-mode for serpent-avx
xfrm: add rfc4494 AES-CMAC-96 support
crypto: add CMAC support to CryptoAPI
crypto: testmgr - add empty test vectors for null ciphers
crypto: testmgr - add AES GMAC test vectors
crypto: gcm - fix rfc4543 to handle async crypto correctly
crypto: gcm - make GMAC work when dst and src are different
hwrng: timeriomem - added devicetree hooks
...
More multiplatform enablement for ARM platforms. The ones converted in
this branch are:
- bcm2835
- cns3xxx
- sirf
- nomadik
- msx
- spear
- tegra
- ux500
We're getting close to having most of them converted!
One of the larger platforms remaining is Samsung Exynos, and there are
a bunch of supporting patches in this merge window for it. There was a
patch in this branch to a early version of multiplatform conversion,
but it ended up being reverted due to need of more bake time. The
revert commit is part of the branch since it would have required
rebasing multiple dependent branches and they were stable by then.
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Merge tag 'multiplatform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC multiplatform updates from Olof Johansson:
"More multiplatform enablement for ARM platforms. The ones converted
in this branch are:
- bcm2835
- cns3xxx
- sirf
- nomadik
- msx
- spear
- tegra
- ux500
We're getting close to having most of them converted!
One of the larger platforms remaining is Samsung Exynos, and there are
a bunch of supporting patches in this merge window for it. There was
a patch in this branch to a early version of multiplatform conversion,
but it ended up being reverted due to need of more bake time. The
revert commit is part of the branch since it would have required
rebasing multiple dependent branches and they were stable by then"
* tag 'multiplatform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (70 commits)
mmc: sdhci-s3c: Fix operation on non-single image Samsung platforms
clocksource: nomadik-mtu: fix up clocksource/timer
Revert "ARM: exynos: enable multiplatform support"
ARM: SPEAr13xx: Fix typo "ARCH_HAVE_CPUFREQ"
ARM: exynos: enable multiplatform support
rtc: s3c: make header file local
mtd: onenand/samsung: make regs-onenand.h file local
thermal/exynos: remove unnecessary header inclusions
mmc: sdhci-s3c: remove platform dependencies
ARM: samsung: move mfc device definition to s5p-dev-mfc.c
ARM: exynos: move debug-macro.S to include/debug/
ARM: exynos: prepare for sparse IRQ
ARM: exynos: introduce EXYNOS_ATAGS symbol
ARM: tegra: build assembly files with -march=armv7-a
ARM: Push selects for TWD/SCU into machine entries
ARM: ux500: build hotplug.o for ARMv7-a
ARM: ux500: move to multiplatform
ARM: ux500: make remaining headers local
ARM: ux500: make irqs.h local to platform
ARM: ux500: get rid of <mach/[hardware|db8500-regs].h>
...
checkstack reports report_deco_status(), report_ccb_status() as
particularly excessive stack users. Move their lookup tables
off the stack and put them in .rodata.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
commit 2af8f4a "crypto: caam - coccicheck fixes" added error
return values yet neglected to change the type from unsigned.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This removes <mach/hardware.h> and <mach/db8500-regs.h>
from the Ux500, merging them into the local include
"db8500-regs.h" in mach-ux500. There is some impact
outside the ux500 machine, but most of it is dealt with
in earlier patches.
Contains portions of a clean-up patch from Arnd Bergmann.
Cc: Samuel Ortiz <sameo@linux.intel.com>
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Commit 4f31f5b19e
"PM / crypto / ux500: Use struct dev_pm_ops for power management"
add a new line to the driver struct but missed to add a
trailing comma, causing build errors when crypto is
selected. This adds the missing comma.
This was not noticed until now because the crypto block
is not in the ux500 defconfig. A separate patch will
be submitted to fix this.
Cc: <stable@vger.kernel.org> # 3.8.x
Cc: Rafael J. Wysocki <rjw@sisk.pl>
Cc: Magnus Myrstedt <magnus.p.persson@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Fix to return a negative error code from the error handling
case instead of 0, as returned elsewhere in this function.
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This eliminates having an #ifdef returning NULL for the case
when OF is disabled.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Acked-by: Jamie Iles <jamie@jamieiles.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This change is required for post SEC-5.0 devices which have RNG4.
Setting RDB in security configuration register allows CAAM to use the
"Random Data Buffer" to be filled by a single request. The Random Data
Buffer is large enough for ten packets to get their IVs from a single
request. If the Random Data Buffer is not enabled, then each IV causes a
separate request, and RNG4 hardware cannot keep up resulting in lower
IPSEC throughput if random IVs are used.
Signed-off-by: Vakul Garg <vakul@freescale.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
SAHARA2 HW module is included in the i.MX27 SoC from
Freescale. It is capable of performing cipher algorithms
such as AES, 3DES..., hashing and RNG too.
This driver provides support for AES-CBC and AES-ECB
by now.
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Javier Martin <javier.martin@vista-silicon.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This reverts commit 891104ed00.
Current IPsec ESN implementation for authencesn(cbc(aes), hmac(sha))
(separate encryption and integrity algorithms) does not conform
to RFC4303.
ICV is generated by hashing the sequence
SPI, SeqNum-High, SeqNum-Low, IV, Payload
instead of
SPI, SeqNum-Low, IV, Payload, SeqNum-High.
Cc: <stable@vger.kernel.org> # 3.8, 3.7
Reported-by: Chaoxing Lin <Chaoxing.Lin@ultra-3eti.com>
Signed-off-by: Horia Geanta <horia.geanta@freescale.com>
Reviewed-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This reverts commit e763eb699b.
Current IPsec ESN implementation for authencesn(cbc(aes), hmac(sha))
(separate encryption and integrity algorithms) does not conform
to RFC4303.
ICV is generated by hashing the sequence
SPI, SeqNum-High, SeqNum-Low, IV, Payload
instead of
SPI, SeqNum-Low, IV, Payload, SeqNum-High.
Cc: <stable@vger.kernel.org> # 3.8, 3.7
Reported-by: Chaoxing Lin <Chaoxing.Lin@ultra-3eti.com>
Signed-off-by: Horia Geanta <horia.geanta@freescale.com>
Reviewed-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
The Kconfig entry for CAAM's hash algorithm implementations has always
selected CRYPTO_AHASH. But there's no corresponding Kconfig symbol.
It seems it was intended to select CRYPTO_HASH, like other crypto
drivers do. That would apparently (indirectly) select CRYPTO_HASH2,
which would enable the ahash functionality this driver uses.
Signed-off-by: Paul Bolle <pebolle@tiscali.nl>
Reviewed-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
module_platform_driver() makes the code simpler by eliminating boilerplate
code.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
module_platform_driver() makes the code simpler by eliminating boilerplate
code.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
After DMA is complete, the omap_aes_finish_req function is called as
a part of the done_task tasklet. During this its atomic and any calls
to pm functions should not assume they wont sleep.
The patch replaces a call to pm_runtime_put_sync (which can sleep) with
pm_runtime_put thus fixing a kernel panic observed on AM33xx SoC during
AES operation.
Tested on an AM33xx SoC device (beaglebone board).
To reproduce the problem, I used the tcrypt kernel module as:
modprobe tcrypt sec=2 mode=500
Signed-off-by: Joel A Fernandes <joelagnel@ti.com>
Cc: David S. Miller <davem@davemloft.net>
Acked-by: Mark A. Greer <mgreer@animalcreek.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
After DMA is complete, the omap_sham_finish_req function is called as
a part of the done_task tasklet. During this its atomic and any calls
to pm functions should not assume they wont sleep.
The patch replaces a call to pm_runtime_put_sync (which can sleep) with
pm_runtime_put thus fixing a kernel panic observed on AM33xx SoC during
SHA operation.
Tested on an AM33xx SoC device (beaglebone board).
To reproduce the problem, used the tcrypt kernel module as:
modprobe tcrypt sec=2 mode=403
Signed-off-by: Joel A Fernandes <joelagnel@ti.com>
Cc: David S. Miller <davem@davemloft.net>
Acked-by: Mark A. Greer <mgreer@animalcreek.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
If we define dev_dbg(), then there is a possible NULL pointer
dereference.
Signed-off-by: Syam Sidhardhan <s.syam@samsung.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Updates from IP release 0x320 to 0x400:
- add DMA support (previous IP revision use PDC)
- add DMA double input buffer support
- add SHA224 support
Update from IP release 0x400 to 0x410:
- add SHA384 and SHA512 support
Signed-off-by: Nicolas Royer <nicolas@eukrea.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Eric Bénard <eric@eukrea.com>
Tested-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Update from previous IP release (0x600):
- add DMA support (previous IP release use PDC)
Signed-off-by: Nicolas Royer <nicolas@eukrea.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Eric Bénard <eric@eukrea.com>
Tested-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Updates from previous IP release (0x120):
- add cfb64 support
- add DMA double input buffer support
Signed-off-by: Nicolas Royer <nicolas@eukrea.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Eric Bénard <eric@eukrea.com>
Tested-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Pull crypto update from Herbert Xu:
"Here is the crypto update for 3.9:
- Added accelerated implementation of crc32 using pclmulqdq.
- Added test vector for fcrypt.
- Added support for OMAP4/AM33XX cipher and hash.
- Fixed loose crypto_user input checks.
- Misc fixes"
* git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (43 commits)
crypto: user - ensure user supplied strings are nul-terminated
crypto: user - fix empty string test in report API
crypto: user - fix info leaks in report API
crypto: caam - Added property fsl,sec-era in SEC4.0 device tree binding.
crypto: use ERR_CAST
crypto: atmel-aes - adjust duplicate test
crypto: crc32-pclmul - Kill warning on x86-32
crypto: x86/twofish - assembler clean-ups: use ENTRY/ENDPROC, localize jump labels
crypto: x86/sha1 - assembler clean-ups: use ENTRY/ENDPROC
crypto: x86/serpent - use ENTRY/ENDPROC for assember functions and localize jump targets
crypto: x86/salsa20 - assembler cleanup, use ENTRY/ENDPROC for assember functions and rename ECRYPT_* to salsa20_*
crypto: x86/ghash - assembler clean-up: use ENDPROC at end of assember functions
crypto: x86/crc32c - assembler clean-up: use ENTRY/ENDPROC
crypto: cast6-avx: use ENTRY()/ENDPROC() for assembler functions
crypto: cast5-avx: use ENTRY()/ENDPROC() for assembler functions and localize jump targets
crypto: camellia-x86_64/aes-ni: use ENTRY()/ENDPROC() for assembler functions and localize jump targets
crypto: blowfish-x86_64: use ENTRY()/ENDPROC() for assembler functions and localize jump targets
crypto: aesni-intel - add ENDPROC statements for assembler functions
crypto: x86/aes - assembler clean-ups: use ENTRY/ENDPROC, localize jump targets
crypto: testmgr - add test vector for fcrypt
...
Delete successive tests to the same location. The code tested the result
of a previous allocation, that itself was already tested. It is changed to
test the result of the most recent allocation.
A simplified version of the semantic match that finds this problem is as
follows: (http://coccinelle.lip6.fr/)
// <smpl>
@s exists@
local idexpression y;
expression x,e;
@@
*if ( \(x == NULL\|IS_ERR(x)\|y != 0\) )
{ ... when forall
return ...; }
... when != \(y = e\|y += e\|y -= e\|y |= e\|y &= e\|y++\|y--\|&y\)
when != \(XT_GETPAGE(...,y)\|WMI_CMD_BUF(...)\)
*if ( \(x == NULL\|IS_ERR(x)\|y != 0\) )
{ ... when forall
return ...; }
// </smpl>
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Acked-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Fix the compile errors created by commit 2545e8d
(crypto: omap-sham - Add Device Tree Support)
when CONFIG_OF is not defined. This includes
changing omap_sham_get_res_dev() to omap_sham_get_res_of()
and creating an empty version of omap_sham_of_match[].
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Use devm_clk_get() rather than clk_get() to make cleanup paths
more simple.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
The OMAP3 and OMAP4/AM33xx versions of the AES crypto
module support the CTR algorithm in addition to ECB
and CBC that the OMAP2 version of the module supports.
So, OMAP2 and OMAP3 share a common register set but
OMAP3 supports CTR while OMAP2 doesn't. OMAP4/AM33XX
uses a different register set from OMAP2/OMAP3 and
also supports CTR.
To add this support, use the platform_data introduced
in an ealier commit to hold the list of algorithms
supported by the current module. The probe routine
will use that list to register the correct algorithms.
Note: The code being integrated is from the TI AM33xx SDK
and was written by Greg Turner <gkmturner@gmail.com> and
Herman Schuurman (current email unknown) while at TI.
CC: Greg Turner <gkmturner@gmail.com>
CC: Dmitry Kasatkin <dmitry.kasatkin@intel.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Add support for the OMAP4 version of the AES module
that is present on OMAP4 and AM33xx SoCs.
The modules have several differences including register
offsets and how DMA is triggered. To handle these
differences, a platform_data structure is defined and
contains routine pointers, register offsets, and bit
offsets within registers. OMAP2/OMAP3-specific routines
are suffixed with '_omap2' and OMAP4/AM33xx routines are
suffixed with '_omap4'.
Note: The code being integrated is from the TI AM33xx SDK
and was written by Greg Turner <gkmturner@gmail.com> and
Herman Schuurman (current email unknown) while at TI.
CC: Greg Turner <gkmturner@gmail.com>
CC: Dmitry Kasatkin <dmitry.kasatkin@intel.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Use the dma_request_slave_channel_compat() call instead of
the dma_request_channel() call to request a DMA channel.
This allows the omap-aes driver use different DMA engines.
CC: Dmitry Kasatkin <dmitry.kasatkin@intel.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Add Device Tree suport to the omap-aes crypto
driver. Currently, only support for OMAP2 and
OMAP3 is being added but support for OMAP4 will
be added in a subsequent patch.
CC: Dmitry Kasatkin <dmitry.kasatkin@intel.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Remove usage of the private OMAP DMA API.
The dmaengine API will be used instead.
CC: Russell King <rmk+kernel@arm.linux.org.uk>
CC: Dmitry Kasatkin <dmitry.kasatkin@intel.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Add code to use the new dmaengine API alongside
the existing DMA code that uses the private
OMAP DMA API. The API to use is chosen by
defining or undefining 'OMAP_AES_DMA_PRIVATE'.
CC: Russell King <rmk+kernel@arm.linux.org.uk>
CC: Dmitry Kasatkin <dmitry.kasatkin@intel.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Add suspend/resume support to the OMAP AES driver.
CC: Dmitry Kasatkin <dmitry.kasatkin@intel.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Convert the omap-aes crypto driver to use the
pm_runtime API instead of the clk API.
CC: Kevin Hilman <khilman@deeprootsystems.com>
CC: Dmitry Kasatkin <dmitry.kasatkin@intel.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
The AES controller only needs to be reset once and that will
be done by the hwmod infrastructure, if possible. Therefore,
remove the reset code from the omap-aes driver.
CC: Dmitry Kasatkin <dmitry.kasatkin@intel.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Remove the unnecessary pr_info() calls from omap_aes_probe()
and omap_aes_mod_init().
CC: Dmitry Kasatkin <dmitry.kasatkin@intel.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
The data referenced by an interrupt handler should not be freed before the
interrupt is ended. The handler is bfin_crypto_crc_handler. It may refer
to crc->regs, which is released by the iounmap.
Furthermore, the second argument to all calls to free_irq is incorrect. It
should be the same as the last argument of request_irq, which is crc,
rather than crc->dev.
The semantic match that finds the first problem is as follows:
(http://coccinelle.lip6.fr/)
// <smpl>
@fn exists@
expression list es;
expression a,b;
identifier f;
@@
if (...) {
... when any
free_irq(a,b);
... when any
f(es);
... when any
return ...;
}
@@
expression list fn.es;
expression fn.a,fn.b;
identifier fn.f;
@@
*f(es);
... when any
*free_irq(a,b);
// </smpl>
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
We still need to fix up few places for multiplatform support,
but that can proceed separately. Fix the issue by making the
problem drivers depends !ARCH_MULTIPLATFORM for now.
The remaining pieces that are not multiplatform compatible
for omap2+ SoCs are:
1. Some drivers are using custom omap_dm_timer calls
There are two drivers that are directly usign omap hardware
timers for PWM and DSP clocking: drivers/media/rc/ir-rx51.c and
drivers/staging/tidspbridge/core/dsp-clock.c. These can be
fixed for multiplatform by allowing a minimal set of hardware
timers to be accessed, and for some functionality by using the
hrtimer framework.
2. Hardware OMAP4_ERRATA_I688 needs to be fixed up
This can't be enabled for multiplatform configurations in
it's current form. It may be possible to fix it up to do
instruction replacement early on during init. Luckily it
looks like this errata does not seem to get hit with
mainline kernel code alone at least currently.
3. Legacy header needed for omap-sham.c
Looks like it still needs mach/irqs.h for omap1 that
does not exist for multiplatform systems. Just ifdef
it for now.
4. Mailbox is waiting to get moved to drivers
Disable it for now to avoid adding a dependency to the
mailbox patches.
Cc: Timo Kokkonen <timo.t.kokkonen@iki.fi>
Cc: Sean Young <sean@mess.org>
Cc: "Víctor Manuel Jáquez Leal" <vjaquez@igalia.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Mauro Carvalho Chehab <mchehab@redhat.com>
Cc: Omar Ramirez Luna <omar.ramirez@ti.com>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
[tony@atomide.com: updated to disable mailbox]
Signed-off-by: Tony Lindgren <tony@atomide.com>
The OMAP4/AM33xx version of the SHAM crypto module
supports SHA224 and SHA256 in addition to MD5 and
SHA1 that the OMAP2 version of the module supports.
To add this support, use the platform_data introduced
in an ealier commit to hold the list of algorithms
supported by the current module. The probe routine
will use that list to register the correct algorithms.
Note: The code being integrated is from the TI AM33xx SDK
and was written by Greg Turner <gkmturner@gmail.com> and
Herman Schuurman (current email unknown) while at TI.
CC: Greg Turner <gkmturner@gmail.com>
CC: Dmitry Kasatkin <dmitry.kasatkin@intel.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Add support for the OMAP4 version of the SHAM module
that is present on OMAP4 and AM33xx SoCs.
The modules have several differences including register
offsets, hardware XORing, and how DMA is triggered.
To handle these differences, a platform_data structure
is defined and contains routine pointers, register offsets,
bit shifts within registers, and flags to indicate whether
the hardware supports XORing and provides SHA1 results in
big or little endian. OMAP2/OMAP3-specific routines are
suffixed with '_omap2' and OMAP4/AM33xx routines are suffixed
with '_omap4'.
Note: The code being integrated is from the TI AM33xx SDK
and was written by Greg Turner <gkmturner@gmail.com> and
Herman Schuurman (current email unknown) while at TI.
CC: Greg Turner <gkmturner@gmail.com>
CC: Dmitry Kasatkin <dmitry.kasatkin@intel.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Use the dma_request_slave_channel_compat() call instead of
the dma_request_channel() call to request a DMA channel.
This allows the omap-sham driver use different DMA engines.
CC: Dmitry Kasatkin <dmitry.kasatkin@intel.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Add Device Tree suport to the omap-sham crypto
driver. Currently, only support for OMAP2 and
OMAP3 is being added but support for OMAP4 will
be added in a subsequent patch.
CC: Dmitry Kasatkin <dmitry.kasatkin@intel.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Remove usage of the private OMAP DMA API.
The dmaengine API will be used instead.
CC: Russell King <rmk+kernel@arm.linux.org.uk>
CC: Dmitry Kasatkin <dmitry.kasatkin@intel.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Add code to use the new dmaengine API alongside
the existing DMA code that uses the private
OMAP DMA API. The API to use is chosen by
defining or undefining 'OMAP_SHAM_DMA_PRIVATE'.
This is a transitional change and the code that uses
the private DMA API will be removed in an upcoming
commit.
CC: Russell King <rmk+kernel@arm.linux.org.uk>
CC: Dmitry Kasatkin <dmitry.kasatkin@intel.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Add suspend/resume support to the OMAP SHAM driver.
CC: Dmitry Kasatkin <dmitry.kasatkin@intel.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Convert the omap-sham crypto driver to use the
pm_runtime API instead of the clk API.
CC: Kevin Hilman <khilman@deeprootsystems.com>
CC: Dmitry Kasatkin <dmitry.kasatkin@intel.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Remove the unnecessary pr_info() call in omap_sham_mod_init().
CC: Dmitry Kasatkin <dmitry.kasatkin@intel.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
CONFIG_HOTPLUG is going away as an option. As a result, the __dev*
markings need to be removed.
This change removes the use of __devinit, __devexit_p, __devinitdata,
and __devexit from these drivers.
Based on patches originally written by Bill Pemberton, but redone by me
in order to handle some of the coding style issues better, by hand.
Cc: Bill Pemberton <wfp5p@virginia.edu>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Kent Yoder <key@linux.vnet.ibm.com>
Cc: Jamie Iles <jamie@jamieiles.com>
Cc: Kim Phillips <kim.phillips@freescale.com>
Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Cc: Alex Porosanu <alexandru.porosanu@freescale.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Pull powerpc update from Benjamin Herrenschmidt:
"The main highlight is probably some base POWER8 support. There's more
to come such as transactional memory support but that will wait for
the next one.
Overall it's pretty quiet, or rather I've been pretty poor at picking
things up from patchwork and reviewing them this time around and Kumar
no better on the FSL side it seems..."
* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (73 commits)
powerpc+of: Rename and fix OF reconfig notifier error inject module
powerpc: mpc5200: Add a3m071 board support
powerpc/512x: don't compile any platform DIU code if the DIU is not enabled
powerpc/mpc52xx: use module_platform_driver macro
powerpc+of: Export of_reconfig_notifier_[register,unregister]
powerpc/dma/raidengine: add raidengine device
powerpc/iommu/fsl: Add PAMU bypass enable register to ccsr_guts struct
powerpc/mpc85xx: Change spin table to cached memory
powerpc/fsl-pci: Add PCI controller ATMU PM support
powerpc/86xx: fsl_pcibios_fixup_bus requires CONFIG_PCI
drivers/virt: the Freescale hypervisor driver doesn't need to check MSR[GS]
powerpc/85xx: p1022ds: Use NULL instead of 0 for pointers
powerpc: Disable relocation on exceptions when kexecing
powerpc: Enable relocation on during exceptions at boot
powerpc: Move get_longbusy_msecs into hvcall.h and remove duplicate function
powerpc: Add wrappers to enable/disable relocation on exceptions
powerpc: Add set_mode hcall
powerpc: Setup relocation on exceptions for bare metal systems
powerpc: Move initial mfspr LPCR out of __init_LPCR
powerpc: Add relocation on exception vector handlers
...
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