Add support for SR PLLs to be voted ON at low temperature threshold and
voted OFF once high threshold is reached. Register with thermal framework
to receive notifications for temperature thresholds and vote for PLLs
accordingly.
Change-Id: Icd689e479899757d821d19853e1600cdf4a84d63
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Add TURBO_HIGH RPM regulator level to support additional
regulator configuration.
Use this voltage level for MX rail on 8976.
CRs-Fixed: 927137
Change-Id: I57c03805a4b3f9c934c534ad5defd512efe9823a
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
DSA clocks used for debug purpose will not be used by any client, remove
the support for the same.
Change-Id: I9465caf45bb5c5c46aa26be1d2c11c46a5c1a322
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Modify gmem clock from gate clock to branch clock and also disable gmem
clock gating.
Change-Id: I574dd3fdceeb819e7f7afdcf5e7e3f044a7657ab
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Clock changes for MSM8976 v1.1 supports new frequency table for SDCC clock
and PCLK1/BYTE1 clock.
Change-Id: If16533206511c64db4a7b7d5388e3a98f1a80677
Signed-off-by: Taniya Das <tdas@codeaurora.org>
The msm_bus driver provides offers a means of managing performance
levels for the buses, fabrics and NoCs, which connect the peripherals
and processes within MSM chipsets.
This snapshot is taken to merge missing changes from msm-3.18 to msm-3.10
Change-Id: If6fff441265716632ee2b8d666cbbdaf5974a34e
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
To support SPM pll management cpu ops are required to be added which needs
re-organization of the code.
SPM child node probe is required for the spm event management to be handled
for the SR2/HF PLL of C0/C1/CCI.
Also make the corresponding device tree changes for the clock name changes
which are added to accommodate the new clock code.
Change-Id: I08e7a7ff367c0ae8ae71f954f2c91858b1e9c386
Signed-off-by: Taniya Das <tdas@codeaurora.org>
USB required to vote for active and sleep NOC clocks both
because when apps power collapse happens, then USB vote is
not honoured. Move the NOC clocks to active and sleep both.
Change-Id: I6528ff0511af8f6209dded1b64a374e02f314283
Signed-off-by: Sujeet Kumar <ksujeet@codeaurora.org>
External snoc qos clock added for 8939 for clients to enable/
disable the clock.
Change-Id: I4083831b2329eadf51866ed3fc9462dbccce2bb7
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Add branch clocks of aps0 and aps1 in the clock list for clients to
enable/disable and set rate.
Change-Id: I06e5d491e93bd0d4b6378e78e554d710ec2220c2
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Introduce a driver that models the cluster and CCI clock trees for
MSM8976, and provides clocks to various drivers that decide the frequency
of those clocks.
Change-Id: Ief20f386b9fa07ebbf84427e70230c1a96b644fa
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Fix QDSS clock type from RPM_SMD to RPM_SMD_QDSS so as to not send any
initial rate for QDSS clock.
The byte1 and pixe1 clock sources from DSI1 only, so cleanup the same.
Change-Id: I2d9593f41e1f9b365830ad859e7c43b0004f215a
Signed-off-by: Taniya Das <tdas@codeaurora.org>
GPLL3 is now controlled by APSS, so configure the pll, also remove the
OXILI_GMEM_CLAMP_IO clamp for oxili gdsc power up sequence.
Cleanup the below
- Venus core1 which is no longer available.
- Fix the clock rate of 64MHz for blsp*_uart1.
Change-Id: I453ad9aa6eecec7fd79060b0d42356440b719663
Signed-off-by: Taniya Das <tdas@codeaurora.org>
GFX has a new rail which needs to be voted when there is a request of clock
rate change from gfx client.
Also add frequency-voltage corner table for gfx clock and populate the OPP
table. Move some of the gfx clocks which were earlier under clock_gcc
device to clock_gcc_gfx device.
Change-Id: I002cd6220c0886230e7c2ece2691e2dffc5aa450
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Add entries for audio clocks required by the external
wcd codec in 8976.
Change-Id: Ice17aa73da66e26e501452ef7fa8cc6c54cc08a8
Signed-off-by: Aravind Kumar <akumark@codeaurora.org>
The current PLL driver for DSI 28nm HPM uses deprecated clock
APIs and supports only PLL0 which will be able to drive the
DSI link clocks for single DSI and split DSI use cases. Add
the support for DSI PLL1 which is needed to drive the DSI
link clocks for a secondary DSI panel for use cases where
two independent DSI panels are involved.
Change-Id: I34b27ad6a73072af4a3501ed142443b735598ff5
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
PMIC clocks are added in the clock list which were missing for the clients
to use.
Change-Id: If8a23ec21f391a9d89e71609b82bf25eaf79b899
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Add support for new audio external clock driver in 8952.
This driver registers to kernel clock framework and
provides clock ops to enable the external (reference) clock
to audio codec hardware. This clock needs to be enabled
for any audio use-cases to run.
Change-Id: I67cd78b801e8354cd7217f94979cf939023fcbcf
Signed-off-by: Aravind Kumar <akumark@codeaurora.org>
Move clock_gcc from dummy clocks to real clocks. As clock_rpm is now part
of clock_gcc, remove clock_rpm device node. Also add node for gfx and mdss
device node.
Move clock_rpm for clients to clock_gcc. MSM8976 rumi supports only dummy
clocks.
Also fix the vdd_dig_levels so as to vote for correct voltage level.
Change-Id: I1176fbc6bbb28f1177e18262f8f9987be7d0deca
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Supports clocks for global clock controller for all peripherals, RPM clock
nodes for bus clocks and pmic xo clocks.
Change-Id: I45fc5eb92b7ac4bf7779974e1ed0711741331e7a
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Apps processor should not access blsp1_uart3 clock. This
is assigned to modem subsystem.
Change-Id: I913930012cc084b44e9cc70e27066e8f2870bf26
Acked-by: Kaushik Sikdar <ksikdar@qti.qualcomm.com>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Define clock structures for sdcc1_ice_core_clk and register
with the clock core. So that it can be used by client drivers.
Change-Id: I15bb0f5e720b04e50f517630be8c9200457e64ad
Signed-off-by: Arun KS <arunks@codeaurora.org>
Add apss_debug_pri_mux to the clock driver.
Add all the cpu clocks to be measured by the driver.
Change-Id: I6eb3963235258f45093e23ca18109a0394692e9a
Acked-by: Liran Mishali <c_liranm@qti.qualcomm.com>
Signed-off-by: Kranthikumar Kurapati <kkurap@codeaurora.org>
Add a UIM device on BLSP_UART1 to FSM9010 based CDP target. This device
controls 4 GPIOs (present, reset, clk and data) via pinctrl driver.
Change-Id: I7184fb00415c3388b773763bca85001bed586260
Acked-by: Ho Lee <holee@qti.qualcomm.com>
Signed-off-by: Venkatesh Yadav Abbarapu <quicvenkat@codeaurora.org>
Add support for all the clocks provided by the DSI1 PLL in preparation
for supporting two independent displays using the two DSI controllers.
Change-Id: I9c9e4cddd23be869d9f16a5c3e1351a88f88699f
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
The byte and pixel RCG clocks can have multiple parents. Use the new clk
ops which support switching between those parents. Update the frequency
table for those RCGs to list out all possible parents and add the missing
ones to the clock list.
Change-Id: Ie926b0d31e79799799146b9f9cf9579c8062300b
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
The byte and pixel RCG clocks can have multiple parents. Use the new clk
ops which support switching between those parents. Update the frequency
table for those RCGs to list out all possible parents and add the missing
ones to the clock list.
Change-Id: Ie3992c2a20820423a35639263f3eec0de166126f
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
Support cpu debug clocks for cluster-0, cluster-1, cci to measure the clock
frequencies using the ring oscillator.
Change-Id: I74941c7c9dd79ff4c6b2a2b50dcb739d4e790d2f
Signed-off-by: Taniya Das <tdas@codeaurora.org>
gcc_oxili_gmem_clk configure wakeup cycle and sleep cycles to number
of clock cycle 1,i.e 0x0 for dynamic power gating.
Change-Id: I28ae61474f818773acb303d1c5f4b4ef635fbb13
Signed-off-by: Taniya Das <tdas@codeaurora.org>
With the official announcement of 8976, remove all references to its
internal code name, and replace them with 8976.
Change-Id: I6d507418e5259908addedf2975e391200b4e0c83
Signed-off-by: Ian Maund <imaund@codeaurora.org>
Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
Add additional parents for the pixel and byte clocks as these can now
switch between those. Also export the sources for the byte and pixel
clocks so that clients can switch between the parents for the relevant
RCGs.
Change-Id: If2c7fe4f12c6ad5a15f13acf71d6dc296b57b665
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
Add additional parents for the pixel and byte clocks as these can now
switch between those. Also export the sources for the byte and pixel
clocks so that clients can switch between the parents for the relevant
RCGs.
Change-Id: I4e1430778dae4a0b77ecc81836b23b6f8c841197
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>
Introduce bus topology for msmterbium. This is a representation
of the bus connections in the SOC and allows the bus driver
to setup bandwidth requests from clients for the paths desired.
Change-Id: Iea841cd77daf1b59fa8d2bb73b58264af0a2e9ea
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
As per latest specification div2 clock controls the mclk of codec, fix the
div_clk1 to div_clk2.
Change-Id: Ife071783f29fa1c28967b5a645da37b8241ac620
Signed-off-by: Taniya Das <tdas@codeaurora.org>
GPLL4 is a voteable pll and it is controlled by RPM.
Modify gpll4 frequency to 1152MHz and make corresponding changes
to the sdcc frequency table.
Change-Id: I1d0c4e78cb8c35c8b1117828cc47ce93875fb51b
Signed-off-by: Arun KS <arunks@codeaurora.org>
Taniya Das
Anirudh Ghayal
Alok Chauhan
Devesh Jhunjhunwala
Sujeet Kumar
Linux Build Service Account
Aravind Kumar
Padmanabhan Komanduru
Rohit Vaswani
Arun KS
Kranthikumar Kurapati
Venkatesh Yadav Abbarapu
Aravind Venkateswaran
Pushkar Joshi
Ian Maund