Adding fix to check the upper limit on the length
of the destination array while copying elements from
source address to avoid stack out of bound error.
Change-Id: Ieb24e8f9b4a2b53fbc9442b25d790b12f737d471
Signed-off-by: Tanwee Kausar <tkausar@codeaurora.org>
Format specifier %p can leak kernel addresses while not valuing the
kptr_restrict system settings. When kptr_restrict is set to (1), kernel
pointers printed using the %pK format specifier will be replaced with 0's.
Change-Id: Iff8d82b12e958b938fc767bf3e8c3a3c8fc65c2a
Signed-off-by: mohamed sunfeer <msunfeer@codeaurora.org>
Check areq before referencing, replace xchg to automic_xchg and
verify return values of set key during SHA operations.
Change-Id: Ife01372ba4990bfefe52b82db4ab33ef76190944
Signed-off-by: Brahmaji K <bkomma@codeaurora.org>
HLOS Crypto driver needs to set CLR_CNTXT bit for operations with
legacy software key registers
Change-Id: Iff482f726d106e99a4006f7077a171da3c7ca9c3
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Adding user passed parameters without check might
lead to Integer overflow and unpredictable system
behaviour.
Change-Id: Iaf8259e3c4a157e1790f1447b1b62a646988b7c4
Signed-off-by: Neeraj Soni <neersoni@codeaurora.org>
Signed-off-by: Yang Guang <guyang@codeaurora.org>
Update clock management details for all the crypto clocks to
fix the suspend resume issue.
Change-Id: I042b021e6737c71f6791dd4aa4f5c4f955b3ad84
Signed-off-by: AnilKumar Chimata <anilc@codeaurora.org>
Add LAPE Support in qce50 driver for 36 bits physical address in BAM
descriptor.
Change-Id: I5500ff5cb3cce717da66075be984b1dfa846f796
Signed-off-by: AnilKumar Chimata <anilc@codeaurora.org>
For crypto device that supports NWD, do single transfer for BAM
consumer and producer pipe for each ciphering request.
Change-Id: I115ea2ea31b6cc6f0efc6c114413e71785c4cf33
Acked-by: Chemin Hsieh <cheminh@qti.qualcomm.com>
Signed-off-by: AnilKumar Chimata <anilc@codeaurora.org>
BAM apps EE value varies from target to target. So platform
specific data needs to provide the value.
Change-Id: Ia66d622ac770a48acd95578adcd4f1564a17232f
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
When the pipe software reset in NDP-BAM is set, the Crypto core
compares its current PIPE_SET_SELECT setting in the CRYPTO_CONFIG
register against the pipe number that is being reset. If the pipe
being reset is part of the currently selected pipe set, the Crypto
core resets as well. This can corrupt an ongoing high speed mode
operation on a different pipe set and cause a core hang. As no design
can have 16 pipe sets, we set PIPE_SET_SELECT value to 0xF, so no
conflict would happen. Besides, HIGH_SPD_DATA_EN_N is set to off to
enable high speed data transfer always. In this case, we change
CRYPTO_CONFIG_RESET value to 0xE01EF.
Change-Id: I9fd158a59b305e46909dbe0fdfd61e835662ca7d
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
The sps_event_notify event debug prints are a somewhat misleading,
as the address printed is not actually the full physical address,
but rather the bottom 32-bits of the physical address. The upper
bits are encoded within sps_iovec.flags, and can be extracted via
the DESC_FULL_ADDR() macro. Use this to print the full address,
and also consolidate duplicated debug prints within a new
print_notify_debug() function.
Change-Id: I34328ff16835ac8f83738f11cade7d792b9807d0
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
Add mutex in qce_open and qce_close to prevent the situation where
iounmap was called by one thread while another one is accessing the
HW CE register with another ioremap.
Change-Id: Iba47834a950a213d8c2b982b3a988020a2ef3338
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Return clk_get error for core_src_clk
Remove enabling other clks for targets that need only core_src_clk
Change-Id: I4749b9f9fff1d6057dbc46aa1bd4c7e50a801ed8
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Crypto operating frequency varies from target to target. So platform
specific data needs to provide the value.
Change-Id: Icea908e958453444ba5a8e882664c8ca43e305e4
Signed-off-by: Mallikarjuna Reddy Amireddy <mamire@codeaurora.org>
One of the crypto clocks is not enabled during device open
path but disabled in the return/closed path results in clk
warnings. This patch fixes the issue with clock flags.
Change-Id: Ic602e93e38fc0242696c4b2d43c892daf7fd123b
Signed-off-by: AnilKumar Chimata <anilc@codeaurora.org>
Crypto core clock enablement is removed from the code to add the support
on msm8994 target as per the clock management, which results in crypto
driver init failure. This patch enables the crypto core clk based on the
flag passed by device tree data.
Change-Id: Ia32bfbc49de8adc5e54e835927c5bd53d7e2a208
Signed-off-by: AnilKumar Chimata <anilc@codeaurora.org>
The functions _ce_get_cipher_cmdlistinfo() and _ce_get_hash_cmdlistinfo()
may return NULL and dereferencing it. This patch fixes the issue with the
proper checks in the driver.
Change-Id: I491d66b0c69347e2cc484160c20655bdd113d67b
Signed-off-by: AnilKumar Chimata <anilc@codeaurora.org>
Add support for multiple crypto instances, new apis are added
to provide information on the crypto instances available.
Crypto uses RPM to enable clocks, this has the fix to rename
the clocks to use the npa node.
Change-Id: Ia568b9ee82235aa686713b039725d27492f4a8e7
Signed-off-by: William Clark <wclark@codeaurora.org>
Crypto module generating wrong hash value for zero length input data
using SHA1 and SHA256 functions. This patch fixes the issue to generate
proper hash value.
Change-Id: I795969cf2d3e3887064d56e35cbb488937051ac8
Signed-off-by: AnilKumar Chimata <anilc@codeaurora.org>
Fixes the crypto BAM issue while running the qcedev_test from usersapce.
BAM command descriptors opcode wrongly going to Crypto BAM hardware. This
patch corrects the issue by seting the opcode to zero.
Also fixes CMAC IOCTL definition with proper struct type.
Change-Id: Ie4195ccd128a8faa98f16ad5ca45ac9bcaef17b9
Signed-off-by: AnilKumar Chimata <anilc@codeaurora.org>
Counter Mask registers are not initialized for 128 bits of counter.
As the result, some test vector of aes(ctr) may fail.
Change-Id: Iccf83aff737d253fa8f8110684e40491bcee7035
Acked-by: Chemin Hsieh <cheminh@qti.qualcomm.com>
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Add support for authenc(hmac(sha256), cbc(des)) and authenc(hmac(sha256),
cbc(aes)) and authenc(hmac(sha256), cbc(des3_ede))
Remove dead code of #ifdef CRYPTO_AEAD_AES_CTR #endif
block in qcrypto and AEAD aes/des/3des ECB mode in qce50. They will
never happen for aead operations.
Stats are cleaned up. Three groups of stats for ABLK, AEAD, and AHASH
operations are managed, and displayed in each group.
Change-Id: I0797c6b3b6596e831b1fb61aa8d4342f19c2b095
Acked-by: Chemin Hsieh <cheminh@qti.qualcomm.com>
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
This patch re-works bus scaling and clk management to respond to
the actual crypto engine usage. The driver suspend/resume are
integrated with overall driver clk and bus management.
Furthermore, two functions are added to the low level crypto driver. Low
level crypto driver is informed to save and restored hardware context if
necessary across PM suspend/resume.
Change-Id: Ic906e0c7e96dee847253d6ef57341d1a38e294cf
Acked-by: Chemin Hsieh <cheminh@qti.qualcomm.com>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
During device probe, device tree is called & the
device tree details are logged - these logs
are now truncated.
Change-Id: I0a6f45cbd4717ded1ef515e3e76452397826d240
Signed-off-by: Hariprasad Dhalinarasimha <hnamgund@codeaurora.org>
Expose APIs to enable qcrypto client to select any specific qcrypto
instance.
Change-Id: Ia96f7fa0f15216c0656aa6dc495db350b3c574a8
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Remove the sps header file from older location as sps
driver and clients need to use new header file from
new location include/linux.
Resolve the warnings/errors from client drivers due to
new sps header changes.
Change-Id: I1cdb87756abf3425a9bb5d8bf89cd1aa03a01716
Signed-off-by: Dipen Parmar <dipenp@codeaurora.org>
Upstream prefers existing drivers be converted to support multiplatform
kernels. This requires drivers to be located in directories that
contain generic functionality instead of specific mach directories.
Move the socinfo driver into drivers/soc/qcom and update the initcall
levels to satisfy dependencies.
Change-Id: If195cd793d84867d371f25136a88f2a7ce239500
Signed-off-by: Xiaocheng Li <lix@codeaurora.org>
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
If ce clock is not disabled in suspend state, memory may be corrupted
and device can not wake up. We add an optional flag "clk_mgmt_sus_res"
for qcrypto driver. This flag indicates if the ce clocks need to be
disabled in suspend function and enabled in resume function of qcrypto
driver. When the flag is set, we disable the clocks that are not disabled
in suspend function and re-enable them again in resume function.
Change-Id: I23be38b2765c0cc5f3ed41d65f8e4ae8a9372d18
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Add optional crypto algorithm flags to indicates if to use SW crypto
algorithms instead of HW algorithms. Based on it, we then rename and
register crypto algorithms to be qualcomm specific to prevent clashing
with the default SW implementation of the algorithms used by dm_crypt
module. (used for disk encryption).
Change-Id: I39badf22581791c502a247f8f37123f513b8c77e
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
The break is missing in the switch-case branch of writing xts du size,
this leads to incorrect xts du size setting.
Change-Id: I288c3d30cc3d59eb28672be32aa57819971ca97f
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Hardcoding key length to a constant value results in overwriting
command element information in the command descriptor beyond what
is allocate for the key information in the command element list.
This results in corruption of the command list in the case where
command descriptors are used for configuring crypto registers and
needlessly writing to key registers that are not relevant to the
operation (when writing to registers directly), and thus leads to
crypto operation failures. Fix is to use the key length based on
what is requested by the client.
Change-Id: Ibd625dc7a438fac84b13588700bf472004e246d5
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
This reverts commit 8d175c9d77, which
release pbam memory when an error occurs. However, on a device with
multiple ce, pbam memory is shared by multiple pce_dev, it can only
be freed when the reference count goes to zero, and can not be
released it if reference count is not zero when an error occurs.
The previous implementation on bam_release was correct, so we
revert commit 8d175c9d77.
Change-Id: Ibc3b83dd46ea087c7a0084d032d96a2848f6baf5
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Architecutural changes in the ARM Linux kernel tree mandate the
eventual removal of the mach-* directories. Move the
mach/clk-provider and mach/clk header to include/linux/clk.
Change-Id: I495f8332bf5d0d09ccfb236c819dea2bacb13542
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
change physical address type to support LPAE for crypro drivers on
APQ8084
Change-Id: I2a85c5db9d131c3be469a5f6b322bc3c4a317400
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Release pmab memory when an error occurs as well.
Change-Id: I7aa13d5a03edbdfa806345039459feaeac6e7a11
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
hmac-sha1 and hamc-sha256 have variable mac key up to a block size.
If user provides a key that is less than the block size, the
key should be padded with zero to the block size before it is
given to the hw.
This padding was not done properly in the driver.
When switch engine between ahash hmac(sha1), hmac(sha256),
and ipsec, problem may happen. ipsec takes 20 bytes of key.
The generated digested data is wrong, even though everything looks
fine from driver. ipsec may fail.
Furthermore, this patch cleanup the driver to do proper setup of
hardware to use hw key or pipe key.
Change-Id: I128eca5a1ac4df326ea1ca9aef2bf27323c1c82f
Acked-by: Chemin Hsieh <cheminh@qti.qualcomm.com>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Kasumi/snow-3g f8/f9 are defined by 3gpp, as the algorithms for
UMTS, and LTE for over the air ciphering and integrity. The
algorithms are supported by crypto 5 hardware. This patch
enables qce50 driver to provide Kasumi/snow-3g f8/f9
ciphering and integrity services.
Change-Id: I7b157e7f178cbe869dcb686a417ac8a5cd4a648a
Acked-by: hemin Hsieh <cheminh@qti.qualcomm.com>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Based on the context flags set by client, set XTS_DU_SIZE
register to sector size of 1KB, or the actual total length
of the packet.
Change-Id: Id461a27013f99301c3ca9e714f397f33c3f6ba03
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
In some platforms such as fsm9900, multiple instances of qce50 hw
may be supported. Each qce50 HW has an ndp-bam. Each qce50 HW
can support multiple instances of qce_dev platform device.
Each qce_dev has its own configured pipe set and associated qce50 HW,
defined by crypto-base and bam-pipe-pair fields in the device tree files.
This patch based on io address, it decides to create a new qce50 hw
instance or use the existing known instance at device probe time.
Furthermore, this patch does iomap for only once for each HW BAM instance
to avoid issue with bam driver. If modprobe, and rmmod of qcedev,
and qcrypto are not in first in last out order, kernel may crash in
bam driver in the last rmmod.
This saves virtual space for IO if multiple instances of qcedev
share the same instance of HW BAM.
Change-Id: I1565b1976981b0512832ff793e0adb29c4be3ccc
Acked-by: Chemin Hsieh <cheminh@qti.qualcomm.com>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
The only version that needs verifiation is major version to ensure
HW CE 5.0 is being used. Minor and step versions checks are not
needed to gate driver loading.
Change-Id: I2052f511f3f2286da78a9c8d4ccf9803fbd6f204
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Tanwee Kausar
mohamed sunfeer
Brahmaji K
Zhen Kong
Neeraj Soni
Manish Kumar
AnilKumar Chimata
Matt Wagantall
Mona Hossain
Mallikarjuna Reddy Amireddy
William Clark
Hariprasad Dhalinarasimha
Dipen Parmar
Xiaocheng Li
Linux Build Service Account
Vikram Mulukutla
Rohit Vaswani