Currently we set CONFIG_CC_OPTIMIZE_FOR_SIZE which suppressed the compiler
warning of unused variables which can lead undefined behavior e.g. memory
corruption and panic. See https://lkml.org/lkml/2013/3/25/347.
This patch fixes all the uninitilized variables in kernel
Bug: 33353384
Test: On device
Signed-off-by: Wei Wang <wvw@google.com>
Change-Id: I0ae1082f447b435d71156d471878ba71aa16c378
Add change to initialise the spread freq variable if the spread
mode is neither down spread nor center. By default, spread mode
is down spread and calculate the spread freq accordingly.
Change-Id: I86408a711dff4d9156ba47d026a60a8b26292772
Signed-off-by: Ashish Garg <ashigarg@codeaurora.org>
WARNING: at ../../../../../../kernel/samsung/msm8976/drivers/clk/qcom/
clock-local2.c:216 rcg_clk_enable+0x50/0xa0()
Attempting to prepare camss_top_ahb_clk_src before setting its rate.
Set the rate first!
Change-Id: Ic4c45b5f894f64ba0f159054d3c36de84cea5537
BCR register is required to reset FSUSB controller. So, add support
for the same.
Change-Id: Ibbf71adc97fcd22ddc5dd7e2f4618074c9e0a0af
Signed-off-by: Vijayavardhan Vennapusa <vvreddy@codeaurora.org>
commit ec7957a6aa0aaf981fb8356dc47a2cdd01cde03c upstream.
Despite care take to allocate clocks state containers the
SP810 driver actually just supports creating one instance:
all clocks registered for every instance will end up with the
exact same name and __clk_init() will fail.
Rename the timclken<0> .. timclken<n> to sp810_<instance>_<n>
so every clock on every instance gets a unique name.
This is necessary for the RealView PBA8 which has two SP810
blocks: the second block will not register its clocks unless
every clock on every instance is unique and results in boot
logs like this:
------------[ cut here ]------------
WARNING: CPU: 0 PID: 0 at ../drivers/clk/versatile/clk-sp810.c:137
clk_sp810_of_setup+0x110/0x154()
Modules linked in:
CPU: 0 PID: 0 Comm: swapper/0 Not tainted
4.5.0-rc2-00030-g352718fc39f6-dirty #225
Hardware name: ARM RealView Machine (Device Tree Support)
[<c00167f8>] (unwind_backtrace) from [<c0013204>]
(show_stack+0x10/0x14)
[<c0013204>] (show_stack) from [<c01a049c>]
(dump_stack+0x84/0x9c)
[<c01a049c>] (dump_stack) from [<c0024990>]
(warn_slowpath_common+0x74/0xb0)
[<c0024990>] (warn_slowpath_common) from [<c0024a68>]
(warn_slowpath_null+0x1c/0x24)
[<c0024a68>] (warn_slowpath_null) from [<c051eb44>]
(clk_sp810_of_setup+0x110/0x154)
[<c051eb44>] (clk_sp810_of_setup) from [<c051e3a4>]
(of_clk_init+0x12c/0x1c8)
[<c051e3a4>] (of_clk_init) from [<c0504714>]
(time_init+0x20/0x2c)
[<c0504714>] (time_init) from [<c0501b18>]
(start_kernel+0x244/0x3c4)
[<c0501b18>] (start_kernel) from [<7000807c>] (0x7000807c)
---[ end trace cb88537fdc8fa200 ]---
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Fixes: 6e973d2c43 "clk: vexpress: Add separate SP810 driver"
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Willy Tarreau <w@1wt.eu>
If KTM get a trip threshold trigger notification and if the
temperature stays the same as the recent trip threshold, KTM will
re-activate the recently triggered threshold, resulting in back to
back interrupts. To avoid this add support in KTM to maintain the
recently triggered threshold state and then re-active the threshold
based on the last threshold trip.
This state is updated for mitigation features like VDD MX retention,
CX phase control, VDD restriction, OCR monitor and external clients
like CPR low temperature monitor etc.
CRs-Fixed: 969112 972634
Change-Id: I44c0a93e1507a9f0b8a65e5c2ce5a98962bb335b
Signed-off-by: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
The frequency precision for few clocks usb/jpeg needs to be updated
to match the fmax corner voting, which otherwise could lead to higher CX
voting.
Change-Id: I10dccbb733941d6f5bf89d5eb055ea0cba110fae
Signed-off-by: Taniya Das <tdas@codeaurora.org>
The PLLs do not require to support fractional mode, so remove the flags
which enable fractional mode.
Change-Id: I551d77082fd3ee8ad02324ac747636632a7bb309
Signed-off-by: Taniya Das <tdas@codeaurora.org>
The current implementation would check for the parent rate and decide the
handoff state of the clock, which is not true for mux clocks. With this
logic the function returns 'enabled' even when the clock downstream of this
clock is disabled. The handoff code will unnecessarily enable the current
parent of this clock.
If this function always returns 'disabled' and a clock downstream is on,
the clock handoff code will bump up the ref count for this clock and its
current parent as necessary. The clocks without an actual HW gate can
always return handoff disabled.
Change-Id: I1f06842e2761b336b49a9390a556064de44f2e36
Signed-off-by: Taniya Das <tdas@codeaurora.org>
As gcc_clock_dev is true only in case of 8952 and when thermal is enabled,
print the information only when thermal is present.
Change-Id: Ie8ee24205a919ab38e0a0e16aa0391492f63c29e
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Add support for SR PLLs to be voted ON at low temperature threshold and
voted OFF once high threshold is reached. Register with thermal framework
to receive notifications for temperature thresholds and vote for PLLs
accordingly.
Change-Id: Icd689e479899757d821d19853e1600cdf4a84d63
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Currently clock driver would try to get all the supported clock rates and
add to OPP framework. Avoid this by adding only the required fmaxes to opp
for clients to extract freq/voltage.
Change-Id: I7bd1de1a67da819f487ea1a7d79e326bb15bfbca
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Occasionally, SR/HF rate PLLs may fail to achieve a lock, and the
output frequency may not match what software expects after configuring
a L value for a certain frequency. If the PLL fails to lock, that is,
the lock detection bit does not go high even after waiting for the
mandated amount of time, record additional PLL debug information in the
kernel log before panic().
Also update the SR PLL power up sequence to assert PLL_RESET_N and
PLL_BYPASSNL together.
Change-Id: Ib98d9b64cc8c8c11138ba75dea9eac649921c1e2
Signed-off-by: Taniya Das <tdas@codeaurora.org>
As per the DSI programming guide, the generated VCO clock comes out
to be same as the calculated vco clock rate as per the below equations.
div_fb = calc_vco_clk / ref_clk_to_pll
generated_vco_clk = div_fb * ref_clk_to_pll
But due to precision loss during implementation of this, some of the
DSI PLL register values might slightly deviate from the expected
values. Add change to fix this by equating the generated VCO clock to
same value as calculated VCO rate.
Change-Id: I478f45766c50ea88c102a87f95be47ec79a74b9a
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
Add change to support the MDSS PLL Spread spectrum clock feature.
This is helpful in avoiding EMI issues of DSI PLL with other
subsystems.
Change-Id: I950c91e2c0955044bf33ce4b4343d1820a945d97
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
Update the VDD classes voting for pm8950_s6* regulators to consider INT_MAX
as regulator max_threshold while calling regulator_set_voltage API.
Change-Id: Id31149d756fd987206100b0a1c31439e96fe4ce6
Signed-off-by: Jaydeep Sen <jsen@codeaurora.org>
Change PM QoS Latency value from 300 to 250 US. This is required
to remove gpll0 vote from APPS when it goes to power collapse with
SPM sequence.
Change-Id: Ifdc50d172b084578c2a15e6ce69272136ad884a0
Signed-off-by: Jaydeep Sen <jsen@codeaurora.org>
DSA clocks used for debug purpose will not be used by any client, remove
the support for the same.
Change-Id: I9465caf45bb5c5c46aa26be1d2c11c46a5c1a322
Signed-off-by: Taniya Das <tdas@codeaurora.org>
The order in which frequency is picked up depends on the L value position
in the frequency table. As the L value of 806.4 is lower than 883.2, it
needs to be moved in the frequency table, else the highest L value will be
used by clock driver.
Change-Id: Iadee6a3c46358b8d45bd2c1f78ae905c68e634c1
Signed-off-by: Taniya Das <tdas@codeaurora.org>
New frequency of 600MHz is now supported for gfx3d clock.
Change-Id: I6df5c36f946e06ecc46e0f8e6ef21b6c8d626e95
Signed-off-by: Taniya Das <tdas@codeaurora.org>
The clusters/cci which could go to low power mode with gpll frequencies
leaves a hw vote always on irrespective of APSS active or in-active. Move
the frequencies to be derived out of APSS/CCI PLL and SPM could take care
of turning the PLLs off when APSS is in-active.
Change-Id: Id43434c5560dee98fe84d11e2685376e1b8f56c8
Signed-off-by: Taniya Das <tdas@codeaurora.org>
GMEM dynamic clock gating needs to be disabled, so remove the compatible
flag from v3 DTSI and also disable it from SPARE_REG3.
Change-Id: Ie5b98f7c772286b4b4e23268f45159d152ce2f9a
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Modify gmem clock from gate clock to branch clock and also disable gmem
clock gating.
Change-Id: I574dd3fdceeb819e7f7afdcf5e7e3f044a7657ab
Signed-off-by: Taniya Das <tdas@codeaurora.org>
commit 3294bee87091be5f179474f6c39d1d87769635e2 upstream.
The ">" should be ">=" or we end up reading beyond the end of the array.
Fixes: 6e973d2c43 ('clk: vexpress: Add separate SP810 driver')
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Acked-by: Pawel Moll <pawel.moll@arm.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Clock changes for MSM8976 v1.1 supports new frequency table for SDCC clock
and PCLK1/BYTE1 clock.
Change-Id: If16533206511c64db4a7b7d5388e3a98f1a80677
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Update the delay values present in the DSI PLL lock sequence
for DSI 28nm HPM SoC as per the latest recommended sequence
present in the DSI hardware programming guide for MSM8956.
Change-Id: Ie7a58f77878e7cafc8acb1a063d18d8aad70d36e
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
Add new cpu clock frequencies in the SVS-NOM corners for performance
cluster for better settling frequency.
Change-Id: I926015daf32e13afbd62914fa56cc4be49a94a77
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Currently the pm_qos lock is greater which could allow L2 GDHS to happen
when set_rate is called, reduce it to a lower value.
Change-Id: I1c0401782a81007a39a6b50b8e53768325376c54
Signed-off-by: Taniya Das <tdas@codeaurora.org>
The SVS corner for SDCC1 clock has been updated from 50MHz to 100MHz, so
update the same.
Change-Id: I921424c03115c151471b94d61ea1ea85a30a063c
Signed-off-by: Taniya Das <tdas@codeaurora.org>
To support SPM pll management cpu ops are required to be added which needs
re-organization of the code.
SPM child node probe is required for the spm event management to be handled
for the SR2/HF PLL of C0/C1/CCI.
Also make the corresponding device tree changes for the clock name changes
which are added to accommodate the new clock code.
Change-Id: I08e7a7ff367c0ae8ae71f954f2c91858b1e9c386
Signed-off-by: Taniya Das <tdas@codeaurora.org>
The debug mux value of WCNSS to measure the clock frequency was incorrect,
fix the same.
Change-Id: I04b9ca7410220a0fab6b964d65c4148e8b3074dc
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Add a new spm probe which will add an SPM child node. Also modify hf pll/sr
pll hooks to add the spm event while enabling/disabling HF/SR PLL.
Change-Id: I998aa2953aaf9408aa2175d1a83c85f517bf7953
Signed-off-by: Taniya Das <tdas@codeaurora.org>
SPM event will be asserted/de-asserted when SR2 PLL is disabled/enabled.
This is required so as the SPM hardware could take care of turning on/off
the PLL when APSS moves to low power mode.
Change-Id: Ic6aa18e47eb352a3582f5e278d7bd99e02bdbcfd
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Along with clk-dis-wait-val to 0x5, we need to sleep value of
OXILI_GFX3D_CBCR to be 0x0.
Change-Id: I8732a0d050d7f7ff2fba0d7faec12c38767861aa
Signed-off-by: Taniya Das <tdas@codeaurora.org>
The CLK_DIS_WAIT bits value may differ from the default value of 0x2.
Allow the value to be taken as input from device tree as parameter
'qcom,clk-dis-wait-val'.
Change-Id: I0a42eec47a563acf667fe6dad39fcd8314e4d590
Signed-off-by: Taniya Das <tdas@codeaurora.org>
The pcnoc vote is required only for CPU clock of 8952, add a check for
compatible flag before voting.
Change-Id: I30d49793e866f4151189be69d61087fa2ac6bbff
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Whenever APSS is active, the cpu clocks would need to put an active vote
of 50MHz on peripheral NOC. This would in turn put a vote on GPLL0, which
would help in cases where APPS needs to be out of suspend and gpll0 is off
due to no other subsystem vote.
Also add a device tree property to indicate if this vote is required or
not.
Change-Id: I531480f13013cd89d3866851f8f3bf591f8dc41b
Signed-off-by: Taniya Das <tdas@codeaurora.org>
SDCC client requires the new frequency of 342.85MHz for scaling the MMC
device. Add support for the same
Change-Id: I328adbf636975a8a7307d974974a54619cc7eeca
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Update the PLL enable sequence for DSI 28nm HPM SoC as per
the latest recommended sequence present in the DSI hardware
programming guide for msm8956.
Change-Id: Ifef6389ea072272724e10106a99b4df4f882bd5d
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
Wei Wang
Ashish Garg
syphyr
Luca Stefani
LuK1337
Vijayavardhan Vennapusa
Linus Walleij
Manaf Meethalavalappu Pallikunhi
Taniya Das
Linux Build Service Account
Padmanabhan Komanduru
Jaydeep Sen
Dan Carpenter